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The statistical distribution of the natural threshold voltage (VT$ of 512k-bit NVM circuit arrays has been studied for two different technologies. The major source of the Vm variation is dopant fluctuations of the NVM well. An analytical model for the dopant fluctuations provides excellent agreement with the measured circuit VTO variation and NVM cell mismatch for both technologies.The reliability implications of the VTo variation are considered using charge leakage models for data retention.

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IntroductionAs CMOS technology is scaled to the 90nm node and beyond, silicon nanocrystal nonvolatile memories are receiving increased attention as a replacement for floating gate nonvolatile memories [1,2]. The thin dielectrics in these memories can lead to excessive gate disturb during the read operation. Of primary concern is the loss of electrons of the program state to the gate through the top oxide overlying the nanocrystals. This loss is the result of tunneling due to the high electric field between the gate and the nanocrystals. It has been shown that reducing the natural threshold voltage (V t,nat ) of the memory cell leads to a reduction in gate disturb [3]. Simple reduction of the V t,nat by decreasing the substrate doping concentration can result in severely degraded short channel performance, as well as degraded hot carrier injection (HCI) performance during the program operation. Thus, it is desired to construct a substrate doping profile with a light surface concentration to obtain a low V t,nat , and a heavy doping concentration just below the surface to provide robust short channel performance and good HCI programmability.