Variation tolerant self-adaptive clock generation architecture based on a ring oscillator

Pérez-Puigdemont, Jordi; Calomarde, Antonio; Moll, Francesc

doi:10.1109/socc.2012.6398341

Cited by 2 publications

(3 citation statements)

References 8 publications

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“…Several studies pointed out the ability of ring oscillators to react immediately and without requiring feedback control to any source of variability, and even some proposals have suggested to incorporate them as clock generators [4]- [6]. Nonetheless, none of the previous schemes described how ring oscillators should behave or which constraints they must satisfy.…”

Section: Variability Margins and Static Timing Analysismentioning

confidence: 99%

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Reactive clocks with variability-tracking jitter

Cortadella

Lavagno

López

et al. 2015

2015 33rd IEEE International Conference on Computer Design (ICCD)

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Abstract-The growing variability in nanoelectronic devices, due to uncertainties from the manufacturing process and environmental conditions (power supply, temperature, aging), requires increasing design guardbands, forcing circuits to work with conservative clock frequencies. Various schemes for clock generation based on ring oscillators and adaptive clocks have been proposed with the goal to mitigate the power and performance losses attributable to variability. However, there has been no systematic analysis to quantify the benefits of such schemes and no signoff method has been proposed for timing correctness. This paper presents and analyzes a Reactive Clocking scheme with Variability-Tracking Jitter (RClk) that uses variability as an opportunity to reduce power by continuously adjusting the clock frequency to the varying environmental conditions, and thus, reduces guardband margins significantly. Power can be reduced between 20% and 40% at iso-performance and performance can be boosted by similar amounts at iso-power. Additionally, energy savings can be translated to substantial advantages in terms of reliability and thermal management. More importantly, the technology can be adopted with minimal modifications to conventional EDA flows.

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Section: Variability Margins and Static Timing Analysismentioning

confidence: 99%

“…This idea has been tentatively explored in the past [4]- [6] but no approach with quantifiable benefits has been analyzed. RClk relies on a robust timing model for assembling a suitable Variability-Tracking Ring Oscillator (VTRO) that is used as a clock source (Section III).…”

Section: Introductionmentioning

confidence: 99%

Reactive clocks with variability-tracking jitter

Cortadella

Lavagno

López

et al. 2015

2015 33rd IEEE International Conference on Computer Design (ICCD)

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“…In the same line others propose to use sensors to detect fast PVTA variations to stop the clock until the perturbation ends [4] but, if the variation lasts, the system could be stopped for a long time. We propose a closed loop adaptive system based on a variable length ring oscillator (VLRO) as clock source, which naturally adapts its frequency to dynamic or static PVTA variations, and time-todigital converters (TDCs) as propagation delay sensors, more precisely as logic propagation length sensors, used to tune the length of the VLRO to ensure the adaptation condition: the TDCs worst output should be equal to the input setpoint value [6]. By this way the proposed system can adapt continuously the clock frequency to PVTA variations which can be homogeneous or heterogeneous along the die as well as operate as a dynamic frequency scaling system by changing the input setpoint value.…”

Section: Introductionmentioning

confidence: 99%

All-digital self-adaptive PVTA variation aware clock generation system for DFS

Pérez-Puigdemont

Calomarde

Moll

2014

2014 5th European Workshop on CMOS Variability (VARI)

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An all-digital self-adaptive clock generation system capable of adapt the clock frequency to compensate the effects of PVTA variations on the IC propagation delay and satisfy an externally set propagation length condition is presented. The design uses timeto-digital converters (TDCs) to measure the propagation length and a variable length ring oscillator (VLRO) to synthesize the clock signal. The VLRO naturally adapts its frequency to the PVTA variations suffered by its logic gates while the TDCs are used to track these variations across the chip and modify the VLRO length in order to adapt the clock frequency to them. The system measurements, for a 45nm FPGA, show that it adapts the VLRO length, and therefore the clock frequency, to satisfy the propagation length condition. Measurements also prove the system capabilities to act as a dynamic frequency scaling clock source since the propagation length condition value act as a frequency selection input and a strong linear relation between the input value and the resultant clock period is present.

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Variation tolerant self-adaptive clock generation architecture based on a ring oscillator

Cited by 2 publications

References 8 publications

Reactive clocks with variability-tracking jitter

Reactive clocks with variability-tracking jitter

All-digital self-adaptive PVTA variation aware clock generation system for DFS

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