Various implementations of topographic, sensory, cellular wave computers

Zarándy, Ákos; Foldesy, M.; Szolgay, Péter; Tőkés, Szabolcs; Rekeczky, Csaba; Roska, Tamás

doi:10.1109/iscas.2005.1465957

Cited by 12 publications

(9 citation statements)

References 3 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The performance of the model varies with the array size and the type of algorithm executing (timing and iteration requirements vary). For example, APRON can perform the 'greyscale feedback convolution' task in 180μs, which could be compared with results presented in [3].…”

Section: D) Cellular Neural Networkmentioning

confidence: 99%

“…Cellular processor arrays (CPAs), such as the ones presented in [1][2][3] implement data processing at a fine-grain level of parallelism. Unlike sequential and coarse-grain parallel processing systems, such as multi-core processors [4], which have large and complex instruction sets, CPAs are often comprised of simpler processors, with specific computational ability.…”

Section: Introductionmentioning

confidence: 99%

“…The highly parallel nature of CPAs has lead to their increased use in a variety of fields, where many simple computations must be performed, and local connectivity would usually be a memory access bottleneck, such as vision chips [2], high-speed image processing [1] [5], cellular neural networks [3] and computational neuroscience models [6]. These applications only require simple numerical operations and neighbour communication, but use operations that are applied homogeneously to large data-sets, at high speeds.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A cellular processor array simulation and hardware prototyping tool

Barr

Dudek

2008

2008 11th International Workshop on Cellular Neural Networks and Their Applications

View full text Add to dashboard Cite

We present a software environment for the efficient simulation of cellular processor arrays (CPAs). This software is used to explore algorithms that are designed for CPAs, neuromorphic arrays, multi-layer neural networks and vision chips. The software (APRON) uses a highly optimised core combined with a flexible compiler to provide the user with tools for the prototyping of new array hardware and the emulation of existing devices. We show that software processor arrays can operate at impressive speeds, with high numerical accuracy. APRON can be configured to use additional processing hardware if necessary, and can even be used as the graphical user interface for new or existing CPA systems.

show abstract

Section: D) Cellular Neural Networkmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A cellular processor array simulation and hardware prototyping tool

Barr

Dudek

2008

2008 11th International Workshop on Cellular Neural Networks and Their Applications

View full text Add to dashboard Cite

show abstract

“…In the past 15 years, since the invention of cellular nonlinear network (CNN) [1,2], many algorithms have been published and several hardware realizations have been introduced on the market [3][4][5][6][7]. After the first successfully functioning analog CNN chips (Ace4k, Ace16k and CACE1, sized 64×64, 128×128 and 32×32 [8][9][10]) and systems (e.g.…”

Section: Introductionmentioning

confidence: 99%

Stochastic bitstream‐based CNN and its implementation on FPGA

Rák

Soós

Cserey

2008

Circuit Theory & Apps

View full text Add to dashboard Cite

SUMMARYIn this paper, we present a new type of cellular nonlinear network (CNN) model and FPGA implementation of cellular nonlinear network universal machine. Our approach uses stochastic bitstreams as data carriers. With the help of stochastic data streams more complex nonlinear cell interactions can be realized than conventional CNN hardware implementations have. The accuracy as indexed by bit depth resolution can be improved at the expense of computation time without influencing hardware complexity. Our simulation results prove the universality and utility of the model. Our experimental results show that the proposed model can be implemented on an FPGA hardware.

show abstract

“…The topographic, sensory, cellular wave computer architectures, based on the CNN-UM (universal machine) principle, have been B mn,i j,kl ·u n,kl (n)+h · z m,i j (2) where the number of layers is denoted by p, the state of the cell is equal to its output and limited in the [1, +1] range. It contains processing elements in a square grid, and the time-step value h is inserted into the A and B template matrices.…”

Section: Introductionmentioning

confidence: 99%

Implementation of embedded emulated‐digital CNN‐UM global analogic programming unit on FPGA and its application

Vörösházi

Kiss

Nagy

et al. 2008

Circuit Theory & Apps

View full text Add to dashboard Cite

SUMMARYThe paper addresses the issue of implementing an embedded global analogic programming unit (GAPU) on the reconfigurable emulated-digital cellular neural/nonlinear networks universal machine (CNN-UM) architecture that has been extended by a flexible Xilinx MicroBlaze soft processor core to take full advantage of the joint computing power of high-speed distributed arithmetics and programmability. The implemented GAPU provides a stand-alone operation, which is capable of controlling complex sophisticated CNN analogic algorithms similar to various visual microprocessors, such as the ACE4k, ACE16k, and Bi-i vision systems. The quality of the embedded GAPU implementation is demonstrated by an analogic algorithm, in which sequences of template operations are required. Based on the experiments, several important issues relating to the acceleration efficiency, accuracy, cell size, and area consumption are discussed and compared with different CNN-UM implementations.

show abstract

Various implementations of topographic, sensory, cellular wave computers

Cited by 12 publications

References 3 publications

A cellular processor array simulation and hardware prototyping tool

A cellular processor array simulation and hardware prototyping tool

Stochastic bitstream‐based CNN and its implementation on FPGA

Implementation of embedded emulated‐digital CNN‐UM global analogic programming unit on FPGA and its application

Contact Info

Product

Resources

About