Verification of transient response of linear analog circuits

Balivada, Ashok; Hoskote, Yatin; Abraham, Jacob A.

doi:10.1109/vtest.1995.512615

Cited by 19 publications

(17 citation statements)

References 6 publications

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“…There has been recent applications of equivalence checking on analog designs by digitization of infinite analog state space [22], [23], [24], and model checking by extending temporal logic to capture analog properties [25], [26]. Finally, the prosyd (prosyd.org) project provides an assertion-based run-time monitoring tool supporting STL or PSL properties in analog circuits.…”

Section: Related Workmentioning

confidence: 99%

Modeling and verification of industrial flash memories

Ray

Bhadra²,

Portlock³

et al. 2010

2010 11th International Symposium on Quality Electronic Design (ISQED)

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Abstract-We present a method to abstract, formalize, and verify industrial flash memory implementations. Flash memories contain specialized transistors, e.g., floating gate and split gate devices, which preclude the use of traditional switch-level abstractions for their verification. We circumvent this problem through behavioral abstractions, which allow formalization of the behaviors of the design as interacting state machines. Behavioral abstractions are agnostic to transistor type, making them suitable for formalizing flash memories. We have verified industrial flash memory implementations based on both floating gate and split gate technologies. Our work provides the first formal functional verification results for industrial flash memories.

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Section: Related Workmentioning

confidence: 99%

Modeling and verification of industrial flash memories

Ray

Bhadra²,

Portlock³

et al. 2010

2010 11th International Symposium on Quality Electronic Design (ISQED)

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“…Analog circuit verification approaches in the past have used state space techniques [6,7]. However, these schemes are either limited to linear circuits [6] or can become highly simulation intensive for large analog circuits [7].…”

Section: 1: Analog Circuit Verificationmentioning

confidence: 99%

“…This is a pessimistic estimate since faults tested by a test stimulus are dropped from further consideration. For large m, the second term can be ignored in comparison to the first, so an approximate bound on test generation time would be (6) For structural faults, the number of backtrace invocations n bt can be treated as a constant w.r.t the number of faults, so the complexity of test generator is approximately O(m).…”

Section: 21: Complexity Of the Test Generation Proceduresmentioning

confidence: 99%

Feedback driven backtrace of analog signals and its application to circuit verification and test

Voorakaranam

Chatterjee²

1999

Proceedings 20th Anniversary Conference on Advanced Research in VLSI

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This paper describes a new approach for backtracing analog signals in a circuit. The process of backtracing involves finding the input signal to an analog circuit, from knowledge of its inputoutput behavior and the desired output signal. While previous approaches rely on the transformation of nodal equations of the circuit to accomplish backtrace, the proposed approach derives the input signal using feedback and forward simulation of a modified circuit. Hence any commercial circuit simulator can be used to the implement the backtrace function. DC convergence conditions for the proposed backtrace approach are derived and it is shown that in the absence of hard nonlinearities, the proposed approach converges to the final solution at a quadratic rate. Application of the backtrace approach to DC verification and test of analog circuits is discussed.

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“…Formal verification methods for AMS designs based on equivalence checking [2,14,22], model checking [13,9,3,15], theorem-proving [7,11,10], etc. do not address the problem of verifying integration of large integrated AMS designs.…”

Section: Introductionmentioning

confidence: 99%