Vertical device architecture for 5nm and beyond: Device &amp;amp; circuit implications

Thean, A.; Yakimets, D.; Huynh-Bao, T.; Schuddinck, P.; Sakhare, Sushil; Bardon, M. Garcia; Sibaja-Hernandez, A.; Ciofi, Ivan; Eneman, G.; Veloso, A.; Ryckaert, Julien; Raghavan, Praveen; Mercha, A.; Mocuta, A.; Tőkei, Zs.; Verkest, D.; Wambacq, Piet; Meyer, K. De; Collaert, N.

doi:10.1109/vlsit.2015.7223689

Cited by 33 publications

(15 citation statements)

References 1 publication

Supporting

Mentioning

Contrasting

Order By: Relevance

“…This allows for relaxing of gate length dimensions (and even the nanowire diameter) and still allowing for lateral device scaling by up to 20% for the same node. 17,18 One of the key process differences between a vertical GAA device and a horizontal GAA device (or even a FinFET) is that the gate length and contact alignments switch from being defined lithographically to being defined by deposition and etch back processes. 17 The process control of these new key steps is well suited for scatterometry and MMSE, in particular.…”

Section: Vertical Gate-all-around Transistors: Dummy A-si Etch Backmentioning

confidence: 99%

See 1 more Smart Citation

Perspective: Optical measurement of feature dimensions and shapes by scatterometry

2018

View full text Add to dashboard Cite

Perspective: Optical measurement of feature dimensions and shapes by scatterometryThe use of optical scattering to measure feature shape and dimensions, scatterometry, is now routine during semiconductor manufacturing. Scatterometry iteratively improves an optical model structure using simulations that are compared to experimental data from an ellipsometer. These simulations are done using the rigorous coupled wave analysis for solving Maxwell's equations. In this article, we describe the Mueller matrix spectroscopic ellipsometry based scatterometry. Next, the rigorous coupled wave analysis for Maxwell's equations is presented. Following this, several example measurements are described as they apply to specific process steps in the fabrication of gate-all-around (GAA) transistor structures. First, simulations of measurement sensitivity for the inner spacer etch back step of horizontal GAA transistor processing are described. Next, the simulated metrology sensitivity for sacrificial (dummy) amorphous silicon etch back step of vertical GAA transistor processing is discussed. Finally, we present the application of plasmonically active test structures for improving the sensitivity of the measurement of metal linewidths.

show abstract

Section: Vertical Gate-all-around Transistors: Dummy A-si Etch Backmentioning

confidence: 99%

“…18 Channel doping is first done to define the source, gate, and drain regions for N and P type transistors followed by nanowire patterning and etch. After the nanowires are etched, there are 2 critical deposition-etch back steps that define the drain, gate length, and contact alignments.…”

Section: Vertical Gate-all-around Transistors: Dummy A-si Etch Backmentioning

confidence: 99%

Perspective: Optical measurement of feature dimensions and shapes by scatterometry

2018

View full text Add to dashboard Cite

show abstract

“…Fig. 54 shows the device architecture of VFET 161 , it has been shown that ~20% area scaling can be achieved with a VFET-based library rather than a finFET-based library in the 5nm node 162 . difficult.…”

Section: Challenges Implementing Beyond Finfet Architecture Optionsmentioning

confidence: 99%

Scaling Challenges for Advanced CMOS Devices

Jacob

Xie

Sung

et al. 2017

Int. J. Hi. Spe. Ele. Syst.

View full text Add to dashboard Cite

The economic health of the semiconductor industry requires substantial scaling of chip power, performance, and area with every new technology node that is ramped into manufacturing in two year intervals. With no direct physical link to any particular design dimensions, industry wide the technology node names are chosen to reflect the roughly 70% scaling of linear dimensions necessary to enable the doubling of transistor density predicted by Moore's law and typically progress as 22nm, 14nm, 10nm, 7nm, 5nm, 3nm etc. At the time of this writing, the most advanced technology node in volume manufacturing is the 14nm node with the 7nm node in advanced development and 5nm in early exploration. The technology challenges to reach thus far have not been trivial. This review addresses the past innovation in response to the device challenges and discusses in-depth the integration challenges associated with the sub-22nm non-planar finFET technologies that are either in advanced technology development or in manufacturing. It discusses the integration challenges in patterning for both the front-end-of-line and back-end-of-line elements in the CMOS transistor. In addition, this article also gives a brief review of integrating an alternate channel material into the finFET technology, as well as next generation device architectures such as nanowire and vertical FETs. Lastly, it also discusses challenges dictated by the need to interconnect the ever-increasing density of transistors.

show abstract

“…The reason for this is because, for very narrow Ge and III-V nanowires, there is a significant loss in their carrier mobility causing them to lose advantage over the Si. [12][13][14] For vertical GAAFETs, this issue of mobility loss can be offset since the gate length is defined in a vertical direction, which allows opting for longer gate lengths, thus relaxing the requirement on nanowire diameter, making it feasible to take the advantage of materials with higher mobility. 12 Fabrication of both vertical and lateral nanowires requires precise control over SiGe etching.…”

Section: Introductionmentioning

confidence: 99%

“…The fabrication of lateral GAAFETs employs SiGe/Si heterostructures, where strain induced by sacrificial SiGe layer increases the carrier mobility of Si nanowires, , thus improving the overall device performance. − At present, Si is still the best choice for a channel material compared to other semiconductors with higher mobility such as Ge and III–V materials. The reason for this is because, for very narrow Ge and III–V nanowires, there is a significant loss in their carrier mobility, causing them to lose advantage over the Si. − For vertical GAAFETs, this issue of mobility loss can be offset since the gate length is defined in a vertical direction, which allows to opt for longer gate lengths, thus relaxing the requirement on nanowire diameter, making it feasible to take advantage of materials with higher mobility …”

Section: Introductionmentioning

confidence: 99%

Selective Wet Etching of Silicon Germanium in Composite Vertical Nanowires

Baraissov

Pacco

Koneti

et al. 2019

ACS Appl. Mater. Interfaces

View full text Add to dashboard Cite

Silicon Germanium (SixGe1-x or SiGe) is an important semiconductor material for the fabrication of nanowire-based gate-all-around transistors in the next-generation logic and memory devices. During the fabrication process, SiGe can either be used as a sacrificial layer to form suspended horizontal Si nanowires or, because of its higher carrier mobility, SiGe can also be used as a possible channel material that replaces Si in both horizontal and vertical nanowires. In both cases, there is a pressing need to understand and develop nanoscale etching processes that enable controlled and selective removal of SiGe with respect to Si. Here, we developed and tested solution-based selective etching processes for SiGe in composite (SiNx/Si0.75Ge0.25/Si) vertical nanowires. The etching solutions were formed by 2 mixing acetic acid (CH3COOH), hydrogen peroxide (H2O2), and hydrofluoric acid (HF). Here, the two chemicals (H2O2 and CH3COOH) react to form highly oxidizing peracetic acid (PAA or). The hydrofluoric acid serves both as a catalyst for PAA formation and as an etchant for oxidized SiGe. Our study shows that an increase in either of the oxidizer concentrations increases the etch rate, and the fastest etch rate of SiGe is associated with the highest PAA concentration. Moreover, using in situ liquid phase TEM imaging, we tested the stability of nanowires during wet etching and identified that SiGe/Si interface to be the weakest plane; we found that once the diameter of the 160-nm-tall Si0.75Ge0.25 nanowire reaches ~15 nm during the etching, the nanowire breaks at or very close to this interface. Our study provides an important insight into the details of the wet etching of SiGe and some of the associated failure modes that are becoming extremely relevant for the fabrication processes as the size of the transistors shrink with every new device-generation.

show abstract

Vertical device architecture for 5nm and beyond: Device & circuit implications

Cited by 33 publications

References 1 publication

Perspective: Optical measurement of feature dimensions and shapes by scatterometry

Perspective: Optical measurement of feature dimensions and shapes by scatterometry

Scaling Challenges for Advanced CMOS Devices

Selective Wet Etching of Silicon Germanium in Composite Vertical Nanowires

Contact Info

Product

Resources

About