Vertical GAAFETs for the Ultimate CMOS Scaling

Yakimets, D.; Eneman, G.; Schuddinck, P.; Huynh-Bao, T.; Bardon, M. Garcia; Raghavan, Praveen; Veloso, A.; Collaert, N.; Mercha, A.; Verkest, D.; Thean, Aaron; Meyer, K. De

doi:10.1109/ted.2015.2414924

Cited by 177 publications

(75 citation statements)

References 14 publications

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“…Vertical nanowire MOSFETs allow for small footprints, as the channel and metal contact lengths are decoupled. It has been suggested that such integration can outperform lateral devices at highly scaled technology nodes [3], [4]. Furthermore, the geometry simplifies the fabrication of a gate-all-around transistor, which ensures good electrostatic control of the transistor channel.…”

Section: Introductionmentioning

confidence: 99%

Self-aligned, gate-last process for vertical InAs nanowire MOSFETs on Si

Berg

Persson

Kilpi

et al. 2015

2015 IEEE International Electron Devices Meeting (IEDM)

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Section: Introductionmentioning

confidence: 99%

Self-aligned, gate-last process for vertical InAs nanowire MOSFETs on Si

Berg

Persson

Kilpi

et al. 2015

2015 IEEE International Electron Devices Meeting (IEDM)

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“…Gate-all-around (GAA) FETs offer the best potential solution to electrostatic control, and can be implemented in a lateral (with one or more lateral wires which are vertically stacked) [94,95] or a vertical configuration [96,97]. The lateral nanowire FETs are closer to FinFETs in terms of processing, circuit design, as well as footprint constraints.…”

Section: Common Challenges: Less Lateral Space Leftmentioning

confidence: 99%

“…The lateral nanowire FETs are closer to FinFETs in terms of processing, circuit design, as well as footprint constraints. The vertical nanowire FETs are less constrained on Lg, spacer thickness, and S/D contact area, as they are oriented vertically and thus should possess even better scalability [96,97]. However, the move towards a vertical architecture will require more disruptive technology and design changes to be considered and implemented.…”

Section: Common Challenges: Less Lateral Space Leftmentioning

confidence: 99%

The Challenges of Advanced CMOS Process from 2D to 3D

Radamson

Zhang

et al. 2017

Applied Sciences

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Abstract:The architecture, size and density of metal oxide field effect transistors (MOSFETs) as unit bricks in integrated circuits (ICs) have constantly changed during the past five decades. The driving force for such scientific and technological development is to reduce the production price, power consumption and faster carrier transport in the transistor channel. Therefore, many challenges and difficulties have been merged in the processing of transistors which have to be dealed and solved. This article highlights the transition from 2D planar MOSFETs to 3D fin field effective transistors (FinFETs) and then presents how the process flow faces different technological challenges. The discussions contain nano-scaled patterning and process issues related to gate and (source/drain) S/D formation as well as integration of III-V materials for high carrier mobility in channel for future FinFETs.

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“…Especially, the vertical surrounding-gate architecture would exhibit geometrical and performance advantages in 7-nm-node devices [5].…”

Section: Introductionmentioning

confidence: 99%

Advances in steep-slope tunnel FETs

Tomioka

Motohisa

Fukui

2016

2016 46th European Solid-State Device Research Conference (ESSDERC)

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Abstract-Tunnel FETs (TFETs) with steep subthreshold slope have been attracting much attention as building blocks for future low-power integrated circuits and CMOS technology devices. Here we report on recent advances in vertical TFETs using III-V/Si heterojunctions. These heterojunctions, which are formed by direct integration of III-V nanowires (NWs) on Si, are promising tunnel junction for achieving steep subthreshold slope (SS). The III-V/Si heterojunction inherently forms abrupt junctions regardless of precise doping technique because the band discontinuity is determined by only the offset of III-V and Si, and depletion region can be controlled by the III-V MOS structure. Thus, good gate-electrostatic control with a large internal electrical field for modulation of tunnel transport can be achieved. Here we repot on recent advances in the vertical TFETs using the III-V NW/Si heterojunction with surroundinggate architecture and demonstrate steep-SS behavior and very low parasitic leakage current.

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Vertical GAAFETs for the Ultimate CMOS Scaling

Cited by 177 publications

References 14 publications

Self-aligned, gate-last process for vertical InAs nanowire MOSFETs on Si

Self-aligned, gate-last process for vertical InAs nanowire MOSFETs on Si

The Challenges of Advanced CMOS Process from 2D to 3D

Advances in steep-slope tunnel FETs

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