Very Low Cost Configurable Hardware Interleaver for 3G Turbo Decoding

Abstract

A very low cost hardware interleaver for 3rd Generation Partnership Project (3GPP) turbo coding algorithm is presented. The interleaver is a key component of turbo codes and it is used to minimize the effect of burst errors in the transmission. Using conventional design methods, it consumes a large part of silicon area in the design of turbo encoder and decoder. The presented hardware interleaver architecture utilizes the algorithmic level hardware simplifications as well as the iterative modulo computation to achieve very low cost solution.After doing the hardware multiplexing and optimization the proposed architecture consumes only 1.5 k gates (without pre-computation) and 2.2 k gates (with precomputation). In both cases the interleaved address is computed every clock cycle except the case of pruning, in which one additional clock cycle is consumed.

Design and Implementation of a Configurable Interleaver/Deinterleaver for Turbo Codes in 3GPP Standard

“…However, it can be noticed that the q i sequences (as mentioned in [2]) are almost the same in most cases and they only differ by one or two elements from other sequences. Based on this observation, we decided to place sub groups of q i sequence into a ROM and then choose one according to the p value.…”

“…There already exists an architecture to compute these operations and it works fine in the pre-computation mode, but in run time mode it fails almost in 12 percent of the block sizes [2]. The problem occurs when q(i)-2p+1>0, in this case the modulo operation cannot be performed correctly (in run time mode); this architecture is shown in Fig.…”

“…In order to develop our interleaver architecture, we based our design on previously reported architecture [2]. Nevertheless, this architecture was improved in some relevant aspects that will be highlighted in the following sections.…”

“…To perform the operations in equation (1), we use the architecture proposed in [2] and shown in Fig. 3.…”

“…In section III the architecture presented in [2] and how it should be completed to manage all sizes of data specified by the standard, as well as how to deal with data and not only with addresses is discussed. Section IV presents the proposed configurable interleaver architecture.…”