VHDL Code Automatic Generator for Systolic Arrays

Tselepis, I. N.; Bekakos, M. P.

doi:10.1109/ictta.2006.1684770

Cited by 3 publications

(2 citation statements)

References 8 publications

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“…Mainly because of its inherent parallelism, pipelining and data processing capabilities, systolic arrays have been adopted for implementing multiple architectures in very different computational-intensive fields, from linear algebra to multimedia applications. In [17], a set of examples of algorithms implemented in SA is reported. In addition, its high regularity, modularity and homogeneity, as well as the regularity of its interconnections, mainly limited to the closer neighbors, make them very suitable to implement scalable solutions based on dynamic reconfiguration, like those provided in [7] and [18].…”

Section: Coprocessor Hardwarementioning

confidence: 99%

Run-Time Scalable Systolic Coprocessors for Flexible Multimedia SoPCs

Otero

Torre

Riesgo

et al. 2010

2010 International Conference on Field Programmable Logic and Applications

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Abstract-Multimedia Systems on Chip have high computational requirements, as well as significant flexibility demands. Flexibility can be related with the reusability of the cores in charge of the execution of computation-intensive tasks, but also with the run-time adaptation of these cores to the execution of time-variable tasks, or to changing system conditions. Among the run-time flexibility requirements of hardware IPs, functional scalability has been identified as an interesting feature. The proposal in this paper is to take advantage of the regularity and the high-processing capability of systolic arrays, to develop runtime functional scalable cores, making use of spatial scalability, by means of replicating and relocating basic processing elements of the array. The relocation process is performed using the dynamic-reconfiguration possibilities offered by commercial FPGAs. In this paper, an architectural template is proposed to develop systolic scalable coprocessors following this approach, together with its corresponding software drivers that may be executed within an embedded processor. In addition, a design flow is proposed to adapt the architectural template to different problems, together with some examples of scalable cores created following this design. This solution provides better results, regarding the reconfiguration time and the memory necessity overhead, compared with other dynamically scalable solutions.

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Section: Coprocessor Hardwarementioning

confidence: 99%

Run-Time Scalable Systolic Coprocessors for Flexible Multimedia SoPCs

Otero

Torre

Riesgo

et al. 2010

2010 International Conference on Field Programmable Logic and Applications

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“…Distributed arithmetic provides scalable solutions to perform arithmetic operations, while systolic architectures can solve full computing-intensive tasks in a broad range of fields. An interesting summary of different systolic arrays, each one for a specific application field, can be found in [11].…”

Section: Introductionmentioning

confidence: 99%

Generic Systolic Array for Run-Time Scalable Cores

Otero

Krasteva

Torre

et al. 2010

Lecture Notes in Computer Science

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Abstract. This paper presents a scalable core architecture based on a generic systolic array. The size of this kind of cores can be adapted in real-time to cover changing application requirements or to the available area in a reconfigurable device. In this paper, the process of scaling the core is performed by the replication of a single processing element using run-time partial reconfiguration. Furthermore, rather than restricting the proposed solution to a given application, it is based on a generic systolic architecture which is adapted using a design flow which is also proposed. The paper includes a related work discussion, the proposal and definition of a systolic array communication approach, which does not require the use of specific macro structures and permits to achieve higher flexibility, and a design flow used to adapt the generic architecture. Further, the paper also includes an image filter application as a simple use case, along with implementation results for Virtex 5 FPGA.

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Development of a control path VHDL code generator for hardware development

Marcus

Brandon

2022

JSE

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The Very High-Speed Integration Circuit HDL (VHDL) is widely used to implement digital electronic systems. The VHDL language can be difficult to learn, so it is necessary to simplify and speed up the process of implementing digital electronic components through a hardware description with a minimal understanding of the VHDL language. This paper entails the design and development of a Graphical User Interface (GUI) capable of generating VHDL code for ControlPaths using specified state transition tables and state diagrams. This application was created using the Matrix Laboratory (MATLAB). Application Builder as the development platform. After development, the system went through unit testing and integration testing, after which acceptance testing was carried out. The results of the acceptance tests showed that the software is very effective in quickly generating VHDL code for ControlPaths.

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VHDL Code Automatic Generator for Systolic Arrays

Cited by 3 publications

References 8 publications

Run-Time Scalable Systolic Coprocessors for Flexible Multimedia SoPCs

Run-Time Scalable Systolic Coprocessors for Flexible Multimedia SoPCs

Generic Systolic Array for Run-Time Scalable Cores

Development of a control path VHDL code generator for hardware development

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