VHDL/S — integrating statecharts, timing diagrams, and VHDL

Helbig, Johannes; Schlör, Rainer; Damm, Werner; Döhmen, Gert; Kelb, Peter

doi:10.1016/0165-6074(93)90197-s

Cited by 13 publications

(1 citation statement)

References 6 publications

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“…An important contribution in this area is the work done by Damm and colleagues at the University of Oldenburg on Symbolic Timing Diagrams (STD's) [9,24,8,16,7]. STD's may be compiled into first-order temporal logic formulae which are then used for model checking.…”

Section: Conclusion and Related Workmentioning

confidence: 99%

Efficient Decompositional Model Checking for Regular Timing Diagrams

Amla

Emerson

Namjoshi³

1999

Lecture Notes in Computer Science

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Abstract. Timing diagrams are widely used in industrial practice to express precedence and timing relationships amongst a collection of signals. This graphical notation is often more convenient than the use of temporal logic or automata. We introduce a class of timing diagrams called Regular Timing Diagrams (RTD's). RTD's have a precise syntax, and a formal semantics that is simple and corresponds to common usage. Moreover, RTD's have an inherent compositional structure, which is exploited to construct an efficient algorithm for model checking a RTD with respect to a system description. The algorithm has time complexity that is linear in the system size and a small polynomial in the representation of the diagram. The algorithm can be easily used with symbolic (BDDbased) model checkers. We illustrate the workings of our algorithm with the verification of a simple master-slave system.

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Section: Conclusion and Related Workmentioning

confidence: 99%