Via-Programmable Structured ASIC Fabric Based on MCML Cells: Design Flow and Implementation

Badel, Stéphane; Hatirnaz, I.; Leblebici, Yusuf; Brauer, E.J.

doi:10.1109/mwscas.2006.382001

Cited by 3 publications

(2 citation statements)

References 6 publications

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“…To regulate a chip layout with the consideration of the advanced process technologies, recent studies have proposed several design methodologies based on via-programmable fabrics [2], [7], high-density transistor arrays [5], precharacterized logic bricks [4], [8], [10], [11], and 1-D cells [12].…”

Section: A Previous Workmentioning

confidence: 99%

1-D Cell Generation With Printability Enhancement

Chen²,

et al. 2013

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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As process technologies advance to the subwavelength era, the 1-D design style is regarded as one of the most effective ways to continue scaling down the minimum feature size. To improve the printability of 1-D cell design, it is essential to insert dummy patterns and optimize line-end gap distribution for each layer. This paper presents novel 1-D cell generation algorithms that simultaneously minimize 1-D cell area and enhance the printability. Experimental results show that the proposed algorithms can effectively and efficiently reduce the number of diffusion gaps, minimize used routing tracks, insert sufficient dummy patterns, and eliminate stage-like line-end gaps without power and timing overhead. Consequently, the 1-D cell area is minimized and the printability of the cell is enhanced. To the best of our knowledge, this is also the first work in the literature that considers line-end gap distribution during 1-D cell generation.Index Terms-Cell generation, gridded design rule, printability enhancement, transistor placement and routing.

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Section: A Previous Workmentioning

confidence: 99%

1-D Cell Generation With Printability Enhancement

Chen²,

et al. 2013

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…Recent work on this topic (excluding memory layout fabrics) could be roughly classified as: 1) gate arrays [6], 2) via programmable fabrics [7]- [8], and 3) precharacterized logic bricks [9]- [10]. In gate arrays, a sea of prefabricated transistors are connected by custom interconnection wires.…”

Section: Introductionmentioning

confidence: 99%

Physical synthesis onto a layout fabric with regular diffusion and polysilicon geometries

Ryzhenko¹,

Burns

2011

Proceedings of the 48th Design Automation Conference

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In this work we propose a regular layout fabric practical for industrial random logic design and present cell synthesis algorithms specialized to this fabric. We show results on an industrial test-case where physical synthesis onto a library of extremely regular cells results in only 7% increase in leakage in comparison to traditional standard cells. We also show that using this fabric based cell synthesis system allows better overall area by allowing more upper layer routing. We achieve a 4% routable die size reduction by simultaneous cell synthesis and custom M1 routing.

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