Video image processing with the Sonic architecture

Haynes, S.D.; Stone, Janice M.; Cheung, Peter Y. K.; Luk, Wayne

doi:10.1109/2.839321

Cited by 46 publications

(28 citation statements)

References 8 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Both the number of logic cells (LCs) and maximum clock frequency are reported. Each of these results corresponds to a single point on the area-error tradeoff curve for the circuit, and have been placed and routed in an Altera Flex10k70RC240-3 device (as used in the Sonic [19] platform) except where otherwise stated. This device is representative of four-input lookup-table-based architectures, which form the core logic fabric of most FPGAs.…”

Section: A Milp Resultsmentioning

confidence: 99%

“…The right-hand side of each inequality (13)- (20) consists of a trivial bound on the left hand side, multiplied by a binary decision variable. These constraints are used in order to allow disjunctions and, thus, implications, for example selecting v1 = 0 in (13) n i 0 n j + p j 0 p i < v1 (n i + p j 0 p i ) (13) v 0 nj + pj 0 pi (1 0 v1)(0nj 0 pi + pj) (14) n i 0 n j + p j 0 p i v2 (0n j + p j 0 p i ) (15) v 0 ni (1 0 v2)(0ni) (16) n j 0 n i + p i 0 p j < v1 (n j 0 p j + p i ) (17) v 0 ni + pi 0 pj (1 0 v1)(1 0ni 0 pj + pi) (18) n j 0 n i + p i 0 p j v2 (0n i + p i 0 p j ) (19) v 0 nj (1 0 v2)(0nj): (20) Note that v is only bounded from below by the constraint given.…”

Section: B Addersmentioning

confidence: 99%

“…Third-party tools are then used to perform the low-level logic synthesis, placement, and routing of the designs. The design-flow for implementation on the Sonic platform [19] is illustrated in Fig. 6, with the Sonic-specific parts shaded.…”

Section: Heuristic Approachmentioning

confidence: 99%

See 2 more Smart Citations

Wordlength optimization for linear digital signal processing

Constantinides

Cheung

Luk

2003

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Self Cite

122

149

View full text Add to dashboard Cite

Abstract-This paper presents an approach to the wordlength allocation and optimization problem for linear digital signal processing systems implemented as custom parallel processing units. Two techniques are proposed, one which guarantees an optimum set of wordlengths for each internal variable, and one which is a heuristic approach. Both techniques allow the user to tradeoff implementation area for arithmetic error at system outputs. Optimality (with respect to the area and error estimates) is guaranteed through modeling as a mixed integer linear program. It is demonstrated that the proposed heuristic leads to area improvements of 6% to 45% combined with speed increases compared to the optimum uniform wordlength design. In addition, the heuristic reaches within 0.7% of the optimum multiple wordlength area over a range of benchmark problems.

show abstract

Section: A Milp Resultsmentioning

confidence: 99%

Section: B Addersmentioning

confidence: 99%

See 1 more Smart Citation

Wordlength optimization for linear digital signal processing

Constantinides

Cheung

Luk

2003

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Self Cite

122

149

View full text Add to dashboard Cite

show abstract

“…Many researches have been conducted on reconfiguration and concluded that reconfigurable computing in FPGA is used to hasten many embedded applications [6]. Most of the image processing machines exploit reconfiguration due to its parallelism feature.…”

Section: Related Workmentioning

confidence: 99%

Reconfigurable Fpga Based Soft-Core Processor for Simd Applications

Maheswari

Pattabiraman

Sharmila

2017

Asian J Pharm Clin Res

View full text Add to dashboard Cite

Objective: The prospective need of SIMD (Single Instruction and Multiple Data) applications like video and image processing in single system requires greater flexibility in computation to deliver high quality real time data. This paper performs an analysis of FPGA (Field Programmable Gate Array) based high performance Reconfigurable OpenRISC1200 (ROR) soft-core processor for SIMD.Methods: The ROR1200 ensures performance improvement by data level parallelism executing SIMD instruction simultaneously in HPRC (High Performance Reconfigurable Computing) at reduced resource utilization through RRF (Reconfigurable Register File) with multiple core functionalities. This work aims at analyzing the functionality of the reconfigurable architecture, by illustrating the implementation of two different image processing operations such as image convolution and image quality improvement. The MAC (Multiply-Accumulate) unit of ROR1200 used to perform image convolution and execution unit with HPRC is used for image quality improvement.Result: With parallel execution in multi-core, the proposed processor improves image quality by doubling the frame rate up-to 60 fps (frames per second) with peak power consumption of 400mWatt. Thus the processor gives a significant computational cost of 12ms with a refresh rate of 60Hz and 1.29ns of MAC critical path delay.Conclusion:This FPGA based processor becomes a feasible solution for portable embedded SIMD based applications which need high performance at reduced power consumptions

show abstract

“…This paper outlines a proposed architecture for an integrated reconfigurable system-on-a-chip, targeted at embedded real-time video image processing. The system is based on the Sonic architecture [1], a PCI-card based system capable of real-time video processing. Our objective is to integrate this system into a single device for embedded video processing applications.…”

Section: Introductionmentioning

confidence: 99%

A Reconfigurable Platform for Real-Time Embedded Video Image Processing

Sedcole

Cheung

Constantinides

et al. 2003

Field Programmable Logic and Application

Self Cite

View full text Add to dashboard Cite

Abstract. The increasing ubiquity of embedded digital video capture creates demand for high-throughput, low-power, flexible and adaptable integrated image processing systems. An architecture for a system-ona-chip solution is proposed, based on reconfigurable computing. The inherent system modularity and the communication infrastructure are targeted at enhancing design productivity and reuse. Power consumption is addressed by a combination of efficient streaming data transfer and reuse mechanisms. It is estimated that the proposed system would be capable of performing up to ten complex image manipulations simultaneously and in real-time on video resolutions up to XVGA.

show abstract

Video image processing with the Sonic architecture

Cited by 46 publications

References 8 publications

Wordlength optimization for linear digital signal processing

Wordlength optimization for linear digital signal processing

Reconfigurable Fpga Based Soft-Core Processor for Simd Applications

A Reconfigurable Platform for Real-Time Embedded Video Image Processing

Contact Info

Product

Resources

About