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Hybrid architectures combining conventional processors with con gurable logic resources enable ecient coordination of control with datapath computation. With integration of the two components on a single device, loop control and data-dependent branching can be handled by the conventional processor, while regular datapath computation occurs on the con gurable hardware. This paper describes a novel pragma-based approach to programming such h ybrid devices. The NAPA C language provides pragma directives so that the programmer or an automatic partitioner can specify where data is to reside and where computation is to occur with statement-level granularity. The NAPA C compiler, targeting National Semiconductor's NAPA1000 chip, performs semantic analysis of the pragma-annotated program and cosynthesizes a conventional program executable combined with a con guration bit stream for the adaptive logic. Compiler optimizations include synthesis of hardware pipelines from pipelineable loops.

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