Automatic allocation of arrays to memories in FPGA processors with multiple memory banks

Gokhale, Maya; Stone, Janice M.

doi:10.1109/fpga.1999.803668

Cited by 38 publications

(18 citation statements)

References 7 publications

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“…The earlier work in [1] describes an algorithm based on a precedence graph without considering the data access patterns. In contrast the approaches in [2,5] map the distinct sections of an array to different RAMs based on the data access patterns of array references and regardless of the schedule.…”

Section: Related Workmentioning

confidence: 99%

“…In this scenario the data references share the available memory bandwidth incurring a latency delay factor of RequiredBandwidth AssignedBandwidth for each array. 1 We assume a speculative execution of all the memory operations regardless of the outcome of the control flow predicates.…”

Section: Analysis Of Data Access Patternsmentioning

confidence: 99%

“…In the DFG edges represent data dependences and nodes (augmented with latency information) represent data accesses or arithmetic/logic operations. Control flow is represented by the graphs corresponding to the two branches of a conditional statement 1 .…”

Section: Analysis Of Critical Pathsmentioning

confidence: 99%

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Memory Parallelism Using Custom Array Mapping to Heterogeneous Storage Structures

Baradaran

Diniz

2006

2006 International Conference on Field Programmable Logic and Applications

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Configurable architectures offer the unique opportunity of customizing the storage allocation to meet specific applications' needs. In this paper we describe a compiler approach to map the arrays of a loop-based computation to internal memories of a configurable architecture with the objective of minimizing the overall execution time. We present an algorithm that considers the data access patterns of the arrays along the critical path of the computation as well as the available storage and memory bandwidth. We demonstrate experimental results of the application of this approach for a set of kernel codes when targeting a Field-Programmable Gate-Array (FPGA). The results reveal that our algorithm outperforms naive and custom data layouts for these kernels by an average of 33% and 15% in terms of execution time, while taking into account the available hardware resources.

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Section: Related Workmentioning

confidence: 99%

Section: Analysis Of Data Access Patternsmentioning

confidence: 99%

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Memory Parallelism Using Custom Array Mapping to Heterogeneous Storage Structures

Baradaran

Diniz

2006

2006 International Conference on Field Programmable Logic and Applications

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“…Gohkale and Stone [12] automatically allocate an array to a particular memory using a technique, called implicit enumeration, coupled with pragmas in the code that must be inserted by the user. They calculate the costs, based on scheduling conflicts, for putting each array in each memory.…”

Section: Related Workmentioning

confidence: 99%

“…This effort differs from our approach. Unlike the algorithmic exhaustive search described in [12], we use a simple greedy algorithm to determine a mapping that minimizes communication between the pipeline stages.…”

Section: Related Workmentioning

confidence: 99%

Coarse-grain pipelining on multiple FPGA architectures

Ziegler

Hall

et al.

Proceedings. 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines

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Reconfigurable systems, and in particular, FPGA-based custom computing machines, offer a unique opportunity to define application-specific architectures. These architectures offer performance advantages for application domains such as image processing, where the use of customized pipelines exploits the inherent coarse-grain parallelism. In this paper we describe a set of program analyses and an implementation that map a sequential and un-annotated C program into a pipelined implementation running on a set of FPGAs, each with multiple external memories. Based on well-known parallel computing analysis techniques, our algorithms perform unrolling for operator parallelization, reuse and data layout for memory parallelization and precise communication analysis. We extend these techniques for FPGA-based systems to automatically partition the application data and computation into custom pipeline stages, taking into account the available FPGA and interconnect resources. We illustrate the analysis components by way of an example, a machine vision program. We present the algorithm results, derived with minimal manual intervention, which demonstrate the potential of this approach for automatically deriving pipelined designs from high-level sequential specifications.

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