Virtualization of reconfigurable coprocessors in HPRC systems with multicore architecture

González, Iván; López-Buedo, Sergio; Sutter, Gustavo; Sanchez-Roman, Diego; Gómez-Arribas, Francisco J.; Aracil, Javier

doi:10.1016/j.sysarc.2012.03.002

Cited by 18 publications

(5 citation statements)

References 10 publications

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“…FPGA OS and Virtualization. Primitives for FPGAs include sharing FPGA fabric [9,14,26,50,51,93], spatial multiplexing [15,28,84,91], context switch [59,77], memory virtualization [1,18,62,96], relocation [40], preemption [60], and interleaved hardware-software task execution [8,30,84,91]. Core techniques include virtualizing FPGA fabric, including regions [71], tasks [73], processing elements [21], IPC-like communication primitives [66], and abstraction layers/overlays [7,33,48,49,85] Extending OS abstractions to FPGAs is an area of active research.…”

Section: Related Workmentioning

confidence: 99%

Compiler-driven FPGA virtualization with SYNERGY

Landgraf

Yang

Lin

et al. 2021

Proceedings of the 26th ACM International Conference on Architectural Support for Programming Languages and Operating Systems

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FPGAs are increasingly common in modern applications, and cloud providers now support on-demand FPGA acceleration in data centers. Applications in data centers run on virtual infrastructure, where consolidation, multi-tenancy, and workload migration enable economies of scale that are fundamental to the provider's business. However, a general strategy for virtualizing FPGAs has yet to emerge. While manufacturers struggle with hardware-based approaches, we propose a compiler/runtime-based solution called Synergy. We show a compiler transformation for Verilog programs that produces code able to yield control to software at sub-clock-tick granularity according to the semantics of the original program. Synergy uses this property to efficiently support core virtualization primitives: suspend and resume, program migration, and spatial/temporal multiplexing, on hardware which is available today. We use Synergy to virtualize FPGA workloads across a cluster of Altera SoCs and Xilinx FPGAs on Amazon F1. The workloads require no modification, run within 3 − 4× of unvirtualized performance, and incur a modest increase in FPGA fabric utilization. CCS CONCEPTS• Hardware → Hardware description languages and compilation; Reconfigurable logic and FPGAs; • Software and its engineering → Compilers; Operating systems.

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Section: Related Workmentioning

confidence: 99%

Compiler-driven FPGA virtualization with SYNERGY

Landgraf

Yang

Lin

et al. 2021

Proceedings of the 26th ACM International Conference on Architectural Support for Programming Languages and Operating Systems

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“…[11] divides the FPGA device into several areas, each dedicated to implement a virtual FPGA accelerator, and partial runtime reconfiguration is used to change one virtual coprocessor without disturbing the others. In [12] several virtual processing units are created out of a single FPGA board by using a timemultiplexed scheme.…”

Section: Related Workmentioning

confidence: 99%

A PCIe DMA engine to support the virtualization of 40 Gbps FPGA-accelerated network appliances

Zazo

López-Buedo

Audzevich

et al. 2015

2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig)

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Network Function Virtualization (NFV) allows creating specialized network appliances out of general-purpose computing equipment (servers, storage, and switches). In this paper we present a PCIe DMA engine that allows boosting the performance of virtual network appliances by using FPGA accelerators. Two key technologies are demonstrated, SR-IOV and PCI Passthrough. Using these two technologies, a single FPGA board can accelerate several virtual software appliances. The final goal is, in an NFV scenario, to substitute conventional Ethernet NICs by networking FPGA boards (such as NetFPGA SUME). The advantage of this approach is that FPGAs can very efficiently implement many networking tasks, thus boosting the performance of virtual networking appliances. The SR-IOV capable PCIe DMA engine presented in this work, as well as its associated driver, are key elements in achieving this goal of using FPGA networking boards instead of conventional NICs. Both DMA engine and driver are open source, and target the Xilinx 7-Series and UltraScale PCIe Gen3 endpoint. The design has been tested on a NetFPGA SUME board, offering transfer rates reaching 50 Gb/s for bulk transmissions. By taking advantage of SR-IOV and PCI Passthrough technologies, our DMA engine provides transfers rate well above 40 Gb/s for data transmissions from the FPGA to a virtual machine. We have also identified the bottlenecks in the use of virtualized FPGA accelerators caused by reductions in the maximum read request size and maximum payload PCIe parameters. Finally, the DMA engine presented in this paper is a very compact design, using just 2% of a Xilinx Virtex-7 XC7VX690T device.

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“…A number of researchers have focused on providing OS support for reconfigurable hardware so as to provide a simple programming model to the user and effective run-time scheduling of hardware and software tasks [22], [23], [24], [25]. A technique to virtualize reconfigurable co-processors in high performance reconfigurable computing (HPRC) systems was presented in [26]. ReconOS [27] is based on an existing embedded OS (eCos) and provides an execution environment by extending a multi-threaded programming model from software to reconfigurable hardware.…”

Section: Related Workmentioning

confidence: 99%

Microkernel hypervisor for a hybrid ARM-FPGA platform

Pham

Jain

Cui³

et al. 2013

2013 IEEE 24th International Conference on Application-Specific Systems, Architectures and Processors

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Reconfigurable architectures have found use in a wide range of application domains, but mostly as static accelerators for computationally intensive functions. Commodity computing adoption has not taken off due primarily to design complexity challenges. Yet reconfigurable architectures offer significant advantages in terms of sharing hardware between distinct isolated tasks, under tight time constraints. Trends towards amalgamation of computing resources in the automotive and aviation domains have so far been limited to non-critical systems, because processor approaches suffer from a lack of predictability and isolation. Hybrid reconfigurable platforms may provide a promising solution to this, by allowing physically isolated access to hardware resources, and support for computationally demanding applications, but with improved programmability and management. We propose virtualized execution and management of software and hardware tasks using a microkernel-based hypervisor running on a commercial hybrid computing platform (the Xilinx Zynq). We demonstrate a framework based on the CODEZERO hypervisor, which has been modified to leverage the capabilities of the FPGA fabric. It supports discrete hardware accelerators, dynamically reconfigurable regions, and regions of virtual fabric, allowing for application isolation and simpler use of hardware resources. A case study demonstrating multiple independent (and isolated) software and hardware tasks is presented.

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Virtualization of reconfigurable coprocessors in HPRC systems with multicore architecture

Cited by 18 publications

References 10 publications

Compiler-driven FPGA virtualization with SYNERGY

Compiler-driven FPGA virtualization with SYNERGY

A PCIe DMA engine to support the virtualization of 40 Gbps FPGA-accelerated network appliances

Microkernel hypervisor for a hybrid ARM-FPGA platform

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