Virtually scaling-free adaptive CORDIC rotator

Abstract

The authors propose a coordinate rotation digital computer (CORDIC) rotator algorithm that eliminates the problems of scale factor compensation and limited range of convergence associated with the classical CORDIC algorithm. In the proposed scheme, depending on the target angle or the initial coordinate of the vector, a scaling by 1 or 1= p 2 is needed that can be realised with minimal hardware. The proposed CORDIC rotator adaptively selects the appropriate iteration steps and converges to the final result by executing on average only 50% of the number of iterations required by the classical CORDIC. Unlike for the classical CORDIC, the value of the scale factor is completely independent of the number of executed iterations. Based on the proposed algorithm, a 16-bit pipelined CORDIC rotator was implemented. The silicon area of the fabricated pipelined CORDIC rotator core is 2.73 mm 2 . This is equivalent to 38 000 inverter gates in the used 0.25 mm BiCMOS technology. The average dynamic power consumption of the fabricated CORDIC rotator is 17 mW at a 2.5 V supply voltage and a 20 Ms=s throughput. Currently, this CORDIC rotator is used as a part of the baseband processor for a project that aims to design a single-chip wireless modem compliant with the IEEE 802.11a standard.

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“…Depending on the domain and quad signals, it generates the final phase angle by addition/subtraction of the accumulated angle to/from or in accordance with the theory developed in [9]. At the same time it asserts an output enable signal for two cycles to indicate to the Combine block that valid data are now present at its input.…”

“…8 shows a flowchart of the virtually scaling-free CORDIC algorithm operating in the vectoring mode. The complete theoretical formulation and performance results can be found in [9] and are omitted here for conciseness.…”

“…In [9], we have developed a virtually scaling-free CORDIC algorithm that eliminates the requirement of the scale factor compensation step, speeds up the CORDIC operation by adaptively executing only the required iterations and exhibits guaranteed convergence over the entire coordinate space. In this formulation it is considered a one-sided vector rotation only as opposed to the classical CORDIC, which approximates the target angle/final vector through to-and-fro vector rotation.…”

“…9(c) shows the basic CORDIC pipeline. For a 16-bit implementation, according to the theory developed in [9], the smallest value for is 4. In order to cover the convergence range of , we have used the stage six times and the stages once each.…”

“…In this formulation it is considered a one-sided vector rotation only as opposed to the classical CORDIC, which approximates the target angle/final vector through to-and-fro vector rotation. The operation of the scaling-free CORDIC can be described by the following equation set [9]: (2) where and are the components of the final output vector, is the accumulated angle up to the th iteration, , is the wordlength, and rounds to the nearest integer towards minus infinity.…”