VLS Grown 4H-SiC Buried P⁺ Layers for JFET Lateral Structures

Abstract

Lateral JFET transistors have been fabricated with N and P-type channels tentatively integrated monolithically on the same SiC wafer. Buried P+SiC layers grown by Vapor-Liquid-Solid (VLS) selective epitaxy were utilized as source and drain for the P-JFET and as gate for the N-JFET. The ohmicity of the contacts, both on VLS grown P+and ion implanted N+layers, has been confirmed by Transfer Length Method (TLM) measurements. A premature leakage current is observed on the P/N junction created directly by the P+VLS gate layer, probably due to imperfect VLS (P+) / CVD (N+) SiC interface.

Classic and alternative methods of p-type doping 4H-SiC for integrated lateral devices

“…Lateral JFET transistors with N-type and Ptype channels have been fabricated, integrated monolithically within the same SiC wafer. Several batches have been fabricated, the first one (detailed in [17]) with P + wells created by Al ion implantation, and the second one (detailed in [18]) with VLS P + wells. The P + wells were utilized as source and drain contacting layers for the P-JFET and as P + gate for the N-JFET.…”