VLSI configurable delay commutator for a pipeline split radix FFT architecture

Garcia, Jesus Luis; Michell, J.A.; Burón, A.M.

doi:10.1109/78.796442

Cited by 16 publications

(16 citation statements)

References 16 publications

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“…By combining the features of the R2 SDF and the R4MDC approaches, the proposed FFT architecture not only can implement the radix-8 FFT algorithm in a 128-point FFT to reduce the number of complex multiplications but also can provide four times the throughput rate, compared with the R2 SDF scheme, as listed in Table III. In addition, the numbers of register excluding the input buffer and complex multiplier used in our scheme are only 38.9% and 44.8% of those in the SRMDC architecture [7]. Although the number of complex adders in our design is greater than that in the others, the cost of complex adders is much less than that of registers and complex multipliers, respectively.…”

Section: B Comparisonmentioning

confidence: 88%

“…Unfortunately, the traditional R2 (Radix-2) MDC architecture cannot provide the available throughput rate unless it raises the work frequency [6]; the R4 (Radix-4) MDC architecture, which needs a power of four, has the limitation on FFT size [6], and the Split-Radix (SR) MDC has higher hardware cost [7]. In addition, the higher radix FFT algorithm is difficult to be implemented in the traditional MDC architecture.…”

Section: Design Issue Of the Fft Processor For The Ofdm-based Uwbmentioning

confidence: 99%

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A 1-GS/s FFT/IFFT processor for UWB applications

Lin

Liu

Lee

2005

IEEE J. Solid-State Circuits

187

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Abstract-In this paper, we present a novel 128-point FFT/IFFT processor for ultrawideband (UWB) systems. The proposed pipelined FFT architecture, called mixed-radix multipath delay feedback (MRMDF), can provide a higher throughput rate by using the multidata-path scheme. Furthermore, the hardware costs of memory and complex multipliers in MRMDF are only 38.9% and 44.8% of those in the known FFT processor by means of the delay feedback and the data scheduling approaches. The high-radix FFT algorithm is also realized in our processor to reduce the number of complex multiplications. A test chip for the UWB system has been designed and fabricated using 0.18-m single-poly and six-metal CMOS process with a core area of 1.76 1.76 mm 2 , including an FFT/IFFT processor and a test module. The throughput rate of this fabricated FFT processor is up to 1 Gsample/s while it consumes 175 mW. Power dissipation is 77.6 mW when its throughput rate meets UWB standard in which the FFT throughput rate is 409.6 Msample/s. Index Terms-Fast Fourier transform (FFT), orthogonal frequency division multiplexing (OFDM), ultrawideband (UWB).

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Section: B Comparisonmentioning

confidence: 88%

Section: Design Issue Of the Fft Processor For The Ofdm-based Uwbmentioning

confidence: 99%

A 1-GS/s FFT/IFFT processor for UWB applications

Lin

Liu

Lee

2005

IEEE J. Solid-State Circuits

187

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“…Pipeline based split-radix FFT architecture has been developed [1] for improving the combinational and sequential delay. This article presents a full custom one-bit slice delay commutator design for pipeline split-radix FFT (SRFFT) architecture.…”

Section: Literature Surveymentioning

confidence: 99%

Low Power 128 Point Split Radix FFT for LTE Application

Shilpha¹

2014

IJMSR

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-In this paper, we describe a processor architecture customized to Split radix FFT algorithm. The proposed architecture supports all FFT sizes, required by the LTE applications. The proposed design is aimed to reduce the area, latency, power and also to reduce the number of computational path in order to speed up FFT processor computation. The proposed low power 128 point split radix FFT architecture applies various periodicity properties of twiddle factors multiplier.We implement the processor in 128-point MDC architecture with split radix algorithm. The processor has been synthesized on a Xilinx ISE 10.1design technology and both energy-efficiency and performance have been evaluated.

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“…Unfortunately, the classical R2MDC architecture does not provide a high processing capability unless its operation frequency is adequately increased 5 ; the R4MDC architecture has the limitation of processing only sequences having lengths equal to an integer power of 4, and the SRMDC architecture has a higher hardware cost 8 . In adition it is difficult to implement algorithms with higher radix using the classical Multi-path architecture.…”

mentioning

confidence: 99%

FPGA realization of a split radix FFT processor

et al. 2007

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Applications based on Fast Fourier Transform (FFT) such as signal and image processing require high computational power, plus the ability to choose the algorithm and architecture to implement it. This paper explains the realization of a Split Radix FFT (SRFFT) processor based on a pipeline architecture reported before by the same authors. This architecture has as basic building blocks a Complex Butterfly and a Delay Commutator. The main advantages of this architecture are:• To combine the higher parallelism of the 4r-FFTs and the possibility of processing sequences having length of any power of two.• The simultaneous operation of multipliers and adder-subtracters implicit in the SRFFT, which leads to faster operation at the same degree of pipeline. The implementation has been made on a Field Programmable Gate Array (FPGA) as a way of obtaining high performance at economical price and a short time of realization. The Delay Commutator has been designed to be customized for even and odd SRFFT computation levels. It can be used with segmented arithmetic of any level of pipeline in order to speed up the operating frequency. The processor has been simulated up to 350 MHz, with an EP2S15F672C3 Altera Stratix II as a target device, for a transform length of 256 complex points.

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VLSI configurable delay commutator for a pipeline split radix FFT architecture

Cited by 16 publications

References 16 publications

A 1-GS/s FFT/IFFT processor for UWB applications

A 1-GS/s FFT/IFFT processor for UWB applications

Low Power 128 Point Split Radix FFT for LTE Application

FPGA realization of a split radix FFT processor

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