Voiding in ultra porous low-k materials proposed mechanism, detection and possible solutions

Jacobs, T.H.; Brennan, K.; Carpio, Ronald A.; Mosig, K.; Lin, J.H.; Mlynko, W.; Fourcher, J.; Bennett, Joe; Wolf, Josh; Augur, R.; Gillespie, Paul

doi:10.1109/iitc.2002.1014944

Cited by 6 publications

(3 citation statements)

References 0 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Among these porous materials, porous SiOCH is the most promising for device application due to its high mechanical strength. [166][167][168] In Fig. 37, the etching rates of various interlayer insulator films are shown as a function of the film density for various etching gases.…”

Section: Etching Of Low-k Materialsmentioning

confidence: 99%

Developments of Plasma Etching Technology for Fabricating Semiconductor Devices

Abe¹,

Yoneda

Fujiwara

2008

jjap

284

163

View full text Add to dashboard Cite

Plasma etching technologies such as reactive ion etching (RIE), isotropic etching, and ashing/plasma cleaning are the currently used booster technologies for manufacturing all silicon devices based on the scaling law. The needs-driven conversion from the wet etching process to the plasma/dry etching process is reviewed. The progress made in plasma etching technologies is described from the viewpoint of requirements for the manufacturing of devices. The critical applications of RIE, isotropic etching, and plasma ashing/cleaning to form precisely controlled profiles of high-aspect-ratio contacts (HARC), gate stacks, and shallow trench isolation (STI) in the front end of line (FEOL), and also to form precise via holes and trenches used in reliable Cu/low-k (low-dielectric-constant material) interconnects in the back end of line (BEOL) are described in detail. Some critical issues inherent to RIE processing, such as the RIE-lag effect, the notch phenomenon, and plasma-induced damage including charge-up damage are described. The basic reaction mechanisms of RIE and isotropic etching are discussed. Also, a procedure for designing the etching process, which is strongly dependent on the plasma reactor configuration, is proposed. For the more precise critical dimension (CD) control of the gate pattern for leading-edge devices, the advanced process control (APC) system is shown to be effective.

show abstract

Section: Etching Of Low-k Materialsmentioning

confidence: 99%

Developments of Plasma Etching Technology for Fabricating Semiconductor Devices

Abe¹,

Yoneda

Fujiwara

2008

jjap

284

163

View full text Add to dashboard Cite

show abstract

“…This could be attributed to reactions of permeated Cu electroplating solution with fluoride residues remaining after plasma etching. 1 Several attempts have been made to avoid this failure. A pore-sealing layer on the porous low-k and a defect-free barrier metal layer formed by chemical vapor deposition ͑CVD͒ were attempted to prevent such low-k film voiding.…”

mentioning

confidence: 99%

A Cu Electroplating Solution for Porous Low-k∕Cu Damascene Interconnects

Shimoyama

Chikaki

Yagi

et al. 2007

J. Electrochem. Soc.

View full text Add to dashboard Cite

A Cu electroplating solution applicable to porous silica ultralow-k films ͑k = 2.1͒ without pore sealing was investigated. A suppressor which causes permeation of Cu electroplating solution was replaced by polyethylene glycol ͑PEG͒ with specific molecular weight ͑Mw͒. Transmission electron microscopy observation revealed that permeation by the Cu solution into the porous silica layer can be suppressed by decreasing the molecular weight of the PEG suppressor in the electroplating solution. A Cu electroplating solution using PEG with Mw = 600 was examined for the low-k porous silica/Cu single-damascene integration process of 300 mm wafer. The filling characteristics in trenches and the uniformity of Cu film thickness were investigated. Interline leakage current on low-k/Cu damascene interconnects was successfully reduced by six orders of magnitude using this Cu plating solution compared with the conventional solution.

show abstract

“…3 However, thinning the barrier metals and increasing the porosity of the low-k films have caused a new failure mode of the porous low-k films such as the voiding phenomena, which could be attributed to the permeation of fluoride residues after plasma etching and water during Cu electroplating. 5 A defect-free barrier metal layer by chemical vapor deposition ͑CVD͒ with atomic layer deposition was proposed to prevent the low-k film voiding. However, the CVD barrier penetrates the porous low-k films.…”

mentioning

confidence: 99%

Influence of Cu Electroplating Solution on Self-Assembled Porous Silica Low-k Films

Shimoyama

Yagi

Chikaki

et al. 2006

J. Electrochem. Soc.

View full text Add to dashboard Cite

The influence of Cu electroplating solution on porous silica low-k films was investigated. The leakage current of the porous silica film with hydrophobic treatment increased significantly after dipping it in Cu electroplating solution. It is found that the Cu electroplating solution permeates the porous silica film owing to its suppressor, which is one of the additives in the Cu electroplating solution, resulting in the increase of leakage current. The permeation characteristics of the electroplating solution were examined using polyethylene glycol ͑PEG͒ as a suppressor. It is found that the leakage current in the porous silica film depends on the molecular weight ͑Mw͒ of PEG. The leakage current increased when the mean Mw of PEG exceeded 1000. The contact angle measurement of the Cu plating solution to the porous silica film shows that the mean Mw of PEG determined the wettability of the porous silica film to the solution. The increase of leakage current in the porous silica low-k film can be suppressed by controlling the mean Mw of PEG less than 1000.

show abstract

Voiding in ultra porous low-k materials proposed mechanism, detection and possible solutions

Cited by 6 publications

References 0 publications

Developments of Plasma Etching Technology for Fabricating Semiconductor Devices

Developments of Plasma Etching Technology for Fabricating Semiconductor Devices

A Cu Electroplating Solution for Porous Low-k∕Cu Damascene Interconnects

Influence of Cu Electroplating Solution on Self-Assembled Porous Silica Low-k Films

Contact Info

Product

Resources

About