Voltage- and current-based fault simulation for interconnect open defects

Abstract

This paper describes a highly accurate and e cient fault simulator for interconnect opens in combinational or full-scan digital CMOS circuits. The analog behavior of the wires with interconnect opens are modeled very e ciently in the vicinity of the defect in order to predict what logic levels the fanout gates will interpret, and whether a su cient IDDQ current will be owing inside the fanout gates. The fault simulation method is based on characterizing the standard cell library with SPICE; using transistor charge equations for the site of the open; using logic simulation for the rest of the circuit; taking four di erent factors that can a ect the voltage of an open into account; and considering the potential oscillation and sequential behavior of interconnect opens. The tool can simulate test vectors for both voltage and current measurements. Simulation results of ISCAS85 layouts using stuck-at and IDDQ test sets are presented.

Investigation into voltage and process variation-aware manufacturing test

“…This model has been verified by measurements on manufactured designs [121,82] and by its ability to predict open defect locations [72]. The amount of charge that can be trapped on a victim net due to a full open is not well known, but Q trapped /C victim to GN D has been assumed to correspond to a variation of [−0.3V, 0.3V ] in [122] and a variation of [−1V, 1V ] in [80] and in [123] the trapped charge has been assumed negligible taking into account the possibility to eliminate this charge during IC fabrication. Due to the uncertainty of the value for the trapped charge it is not possible to fully predict the behaviour of a full open defect [124].…”

“…Intra-gate opens have been studied in [75,76,77,78,71,79], and it has been reported that such defects can cause delay behaviour, can increase IDDQ and can cause static faulty logic behaviour [77]. The focus in Chapter 4 is on full open defects on interconnect, since most open defects occur on interconnect [80]. The considered defect type in Chapter 4 completely separates a net from its driver ( problem" because of its similarities with a classical computer-science problem [85].…”

“…If this current shows a significant increase in the IDDQ current, a current-based test will detect the full open defect. This observation was employed in [80,122]. It should be noted that IDDQ testing does not detect all full open defects, and voltage based testing is useful for the remaining defects.…”

“…Several studies, [123,122,72,80,77,129,75,157,119] and [118], have used a model for full opens that determines the voltage on the victim net (the net that is separated from its driver by the defect) by the following three factors. and two driven inputs in1 and in2 (IN is the set of gate inputs that are driven by the victim net).…”

“…The model in Equation 4.1 was used in [80] for simulation and in [123] it was used to reason about measurements from manufactured test structures and diagnosis. It has been shown in [72] …”