Voltage contrast edge placement estimation for overlay, CD, and local uniformity metrology (Conference Presentation)

Tabery, Cyrus; Rutigliani, Vito; Hastings, Simon; Poortere, Etienne De; Wang, Luke; Leray, Philippe; Schelcher, Guillaume; Wang, Yongjun

doi:10.1117/12.2516613

Cited by 4 publications

(4 citation statements)

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“…To characterize the 28nm-pitch dual damascene process, VCEPE-like test structures [5], in which the viato-metal overlap is changed in small steps, are designed with a variation in the parameters of interest.…”

Section: A Doe Characterizationmentioning

confidence: 99%

Machine learning methods for voltage contrast yield analysis

Cerbu,

Blanco Carballo,

Schleicher

et al. 2024

Metrology, Inspection, and Process Control XXXVIII

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Section: A Doe Characterizationmentioning

confidence: 99%

Machine learning methods for voltage contrast yield analysis

Cerbu,

Blanco Carballo,

Schleicher

et al. 2024

Metrology, Inspection, and Process Control XXXVIII

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“…To characterize the dual damascene process, test structures 7 are designed with a programmed variation of the via-to-metal overlap and of the T2T CD (in small steps), and of the via CD, metal pitch, and metal proximity. Figure 6 shows examples of the parameters in the design of experiments (DoE).…”

Section: Vc Inspectionmentioning

confidence: 99%

Voltage contrast determination of design rules at the limits of EUV single patterning

Blanco Carballo,

De Poortere,

Leray

et al. 2023

J. Micro/Nanopattern. Mats. Metro.

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We have used large-field-of-view voltage contrast metrology to determine the design rules on a pitch 28 nm single-exposure extreme ultra violet dual damascene process, and to study a use case in which two design parameters, metal tip-to-tip critical dimension and via-to-line placement, interact nontrivially in the yield determination. By designing proper test structures, it is possible to determine the different failure mechanisms for the given process integration and determine the patterning cliffs and design rules.

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“…It has been shown that the EPE metric exhibits a stronger correlation with patterning defects compared to individual metrics [2]. Other research indicates that EPE has the potential to serve as an early predictor for yield [3]. Thus, EPE-aware process controller allows contributors from different layers to cross compensate to each other in spatial fingerprint, therefore, enabling the overall improvement of multilayer EPE [4,5].…”

Section: Introductionmentioning

confidence: 99%

Feature grouping to enable edge placement error-aware process control in multi-feature logic use case

Schelcher,

Athayde,

Schoofs

et al. 2024

Metrology, Inspection, and Process Control XXXVIII

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The grouping method assisted EPE-aware control method is being explored in a multi-feature dual layer Logic use case. EPE metric is estimated using angle resolved optical Scatterometry based overlay and electron beam-based metrology (large field of view SEM) for the reconstruction of edge-to-edge distance between the Metal and Via pattern. In the setup phase, EPE sensitivities to dose and focus have been derived using data from a FEM wafer. EPE-aware optimization, using scanner dose and overlay control sub-recipes, outperforms traditional optimization in simulations showing reduced EPE max per die. This improvement suggests a potential increase in device yield through the adoption of EPE-aware control strategies. To verify this performance improvement on wafers, an experiment is needed with minimal wafer to wafer and lot to lot variations which can be achieved by reducing time between lots and increasing the number of wafers measured.

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Voltage contrast edge placement estimation for overlay, CD, and local uniformity metrology (Conference Presentation)

Cited by 4 publications

References 0 publications

Machine learning methods for voltage contrast yield analysis

Machine learning methods for voltage contrast yield analysis

Voltage contrast determination of design rules at the limits of EUV single patterning

Feature grouping to enable edge placement error-aware process control in multi-feature logic use case

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