Voltage/current measurement performance and power supply rejection in all-digital Class-D power amplifiers

Distortion Minimization for Ultra-Low THD Class-D Power Amplifiers

“…All analog-to-digital converters (ADCs) feature an amplitude resolution of 16 bits and a maximum sample rate of 1 MHz (LTC2368-16 and ADS8861), except for the load current ADC, which is an 18-bit, 5 MHz device (AD7960) in order to minimize the intrinsic sensor noise of the load current measurement. All currents are measured using shunt resistors (with isolated ADCs), as this enables a superior noise and distortion performance as compared to integrated solutions [36]. The DC-link and phase voltages (≤ 400 V) are measured using resistive dividers that are optimized for low noise and distortion [36].…”

“…All currents are measured using shunt resistors (with isolated ADCs), as this enables a superior noise and distortion performance as compared to integrated solutions [36]. The DC-link and phase voltages (≤ 400 V) are measured using resistive dividers that are optimized for low noise and distortion [36]. The 5 MHz load current ADC employs oversampling and a 6 th -order anti-aliasing Butterworth filter.…”

“…The 5 MHz load current ADC employs oversampling and a 6 th -order anti-aliasing Butterworth filter. This sensor is capable of measuring THD down to a level of ≈ -110 dB, which is mainly limited by the operational amplifiers in its gain stage and anti-aliasing filter (LT1028, AD8620 and ADA4932) [36]. This is sufficient for the demonstrated performance, as the THD is limited by other factors, such as half-bridge dead time.…”

“…As mentioned in Section II, the low-distortion sensor system for the load current has an intrinsic THD limit of ≈ -110 dB, which is primarily caused by the operational amplifiers of its analog front-end. This restriction could be overcome by reducing the filter complexity by, e.g., increasing the ADC sampling rate [36].…”

Low-Jitter GaN E-HEMT Gate Driver With High Common-Mode Voltage Transient Immunity

“…The digital PWM modulator is clocked with 100 MHz and has (configurable) counter resolutions of 9, 8 and 7 bit, which results in pulse repetition frequencies of 97.7 kHz, 195 kHz and 391 kHz [13]. As the two half-bridges are operated in an open-loop fashion (i.e., no voltages/currents are measured and no feedback is employed), a low-noise 400 V power supply is required as an open-loop switch-mode amplifier is characterized by a low power supply rejection [43], [44]. Otherwise, too much additional noise would be introduced to the half-bridge output voltages which would render the noise contributions from the gate drivers unobservable.…”