Voltage island-driven power optimization for application specific network-on-chip design

Abstract

In this paper, a voltage island aware framework is proposed for low power design of application specific NoC (LPASNoC). Through a three-phase processing including voltage island generation, VI-driven floorplanning and post-floorplan processing, the total power consumption, design cost and total wire length can be optimized. Experimental results show that compared to traditional ASNoC, the proposed method can reduce total core power by about 34.5% and chip area by about 26.8% without increasing communication power.

Mechanism of Energy-Consumption Benchmark State for Coal-Fired Power Units with Varying Boundary

“…Because of the coupling relation and changing characteristic between equipment and system, the additional fuel specific consumption(AFSC) of i S can be divided into [10] :…”

“…Based on the study of Song Zhiping etc. [9] , Wang Ligang [10] considered the equipment coupling relation and change characteristic and put forward a energy-consumption analysis theory. Besides, Wang [11] put forward the concept of "energy-consumption benchmark state" under varying boundary conditions and their parameters parsing, and the benchmark was developed from one or several parameters to the benchmark state level.…”

Communication-aware custom topology generation for VFI network-on-chip

“…Therefore, regular topologies are not sufficient to accommodate recent architectural trends. On the contrary, custom topologies can provide more design optimization opportunities by exploiting the asymmetric properties in both heterogeneous many-core SoC architectures and their associated communication traffic patterns [4,5].…”