VPR 5.0

Luu, Jason; Kuon, Ian; Jamieson, Peter; Campbell, Ted; Ye, Andy; Fang, Wei Mark; Rose, Jonathan

doi:10.1145/1508128.1508150

Cited by 153 publications

(25 citation statements)

References 25 publications

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“…Finally, the outputs of an LC are connected directly to multiplexers in the switch boxes through isolation buffers. This is similar to the architectural assumptions made in the VPR 5.0 tool [12], which is more realistic than using output pin connection boxes. Figure 3 shows an FPGA that has an application composed of two modules, M1 and M2.…”

Section: B Architectural Frameworksupporting

confidence: 55%

An FPGA architecture supporting dynamically controlled power gating

Bsoul

Wilton

2010

2010 International Conference on Field-Programmable Technology

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Abstract-Leakage power is an important component of the total power consumption in FPGAs built using 90 nm and smaller technology nodes. Power gating, in which regions of the chip can be powered down, has been shown to be effective at reducing leakage power. However, previous techniques focus on staticallycontrolled power gating. In this paper, we propose a modification to the fabric of an FPGA that enables dynamically-controlled power gating, in which logic clusters can be selectively powereddown at run-time. For applications containing blocks with large idle times, this could lead to significant leakage power savings. Our architecture utilizes the existing routing fabric and unused input pins of logic clusters to route the power control signals. No modifications to the existing routing algorithms are required to support the new architecture. We study the area and power tradeoffs by varying the basic architecture parameters of an FPGA, and by varying the size of the power gating regions. We also study the leakage energy savings using a model that characterizes an application in terms of its structure and behavior. We show less than 1% of area overhead for a power gating region size of 3X3 logic tiles. Using the application model, we show that up to 40% leakage energy reduction can be achieved using the proposed architecture for different application parameters, not including power dissipated by the power state controller.

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Section: B Architectural Frameworksupporting

confidence: 55%

An FPGA architecture supporting dynamically controlled power gating

Bsoul

Wilton

2010

2010 International Conference on Field-Programmable Technology

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“…3.3 VPR5.0 VPR( [23]) is a toolset, which was developed at the University of Toronto in the late 1990s and is widely "used to perform FPGA architecture and CAD research [24]." The main purpose of VPR is to place logic structures on FPGA devices and to perform an optimized routing based on experimental results.…”

Section: Odin IImentioning

confidence: 99%

“…Those results are mostly not available as they have not been contributed to the project( [24], p1). In [24], VPR 5.0 was introduced and includes the following key features:…”

Section: Odin IImentioning

confidence: 99%

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Visualization support for FPGA architecture exploration

Nasartschuk

Herpers

Kent

2012

2012 23rd IEEE International Symposium on Rapid System Prototyping (RSP)

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Nowadays Field Programmable Gate Arrays (FPGA) are used in many fields of research, e.g. to create prototypes of hardware or in applications where hardware functionality has to be changed more frequently. Boolean circuits, which can be implemented by FPGAs are the compiled result of hardware description languages such as Verilog or VHDL. Odin II is a tool, which supports developers in the research of FPGA based applications and FPGA architecture exploration by providing a framework for compilation and verification. In combination with the tools ABC, T-VPACK and VPR, Odin II is part of a CAD flow, which compiles Verilog source code that targets specific hardware resources. This paper describes the development of a graphical user interface as part of Odin II. The goal is to visualize the results of these tools in order to explore the changing structure during the compilation and optimization processes, which can be helpful to research new FPGA architectures and improve the workflow.ii CONTENTS

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“…Odin II is built to integrate seamlessly with the VPR 5.0 [2] CAD flow, which allows researchers to explore FPGA architectures and CAD algorithms. However, Odin II is inherently a general synthesis framework that can be used to target any CAD flow.…”

Section: Introductionmentioning

confidence: 99%

Odin II - An Open-Source Verilog HDL Synthesis Tool for CAD Research

Jamieson

Kent

Gharibian

et al. 2010

2010 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines

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130

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Abstract-In this work, we present Odin II, a framework for Verilog Hardware Description Language (HDL) synthesis that allows researchers to investigate approaches/improvements to different phases of HDL elaboration that have not been previously possible. Odin II's output can be fed into traditional back-end flows for both FPGAs and ASICs so that these improvements can be better quantified. Whereas the original Odin [1] provided an open source synthesis tool, Odin II's synthesis framework offers significant improvements such as a unified environment for both front-end parsing and netlist flattening. Odin II also interfaces directly with VPR [2], a common academic FPGA CAD flow, allowing an architectural description of a target FPGA as an input to enable identification and mapping of design features to custom features. Furthermore, Odin II can also read the netlists from downstream CAD stages into its netlist data-structure to facilitate analysis. Odin II can be used for a wide range of experiments; in this paper, we show three specific instances of how Odin II can be used by ASIC and FPGA researchers for more than basic synthesis. Odin II is open source and released under the MIT License.

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VPR 5.0

Cited by 153 publications

References 25 publications

An FPGA architecture supporting dynamically controlled power gating

An FPGA architecture supporting dynamically controlled power gating

Visualization support for FPGA architecture exploration

Odin II - An Open-Source Verilog HDL Synthesis Tool for CAD Research

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