$W$-Band BPSK and QPSK Transceivers With Costas-Loop Carrier Recovery in 65-nm CMOS Technology

Multi-Gb/s Analog Synchronous QPSK Demodulator With Phase-Noise Suppression

“…Results from other published demodulators in the literature are included as well for comparison. The presented synchronous demodulator achieves a very high data rate, exceeding those presented in [9] and [15]. Furthermore, based on the measurements with BPSK signals in [10], the presented demodulator can potentially demodulate up to a data rate of 10 Gb/s, and such a high data rate is demonstrated only in [14] and [5].…”

“…It should be noted that such a strong phase-noise cancellation cannot be achieved for feedback-type carrier recovery circuits, such as a Costas loop, as the PLL delay will be typically several orders of magnitude higher than that of the feed-forward topology (cf. [9]). …”

A Novel Quadrature‐Tracking Demodulator for LTE‐A Applications

“…To simplify the receiver's circuitry, various phase-locked loop (PLL)-based coherent demodulators are adopted in wireless communication systems. The most well-known PLL-based coherent demodulator has the Costas architecture [1,[3][4][5]. As depicted in Figure 1, this architecture uses a single PLL with two feedback loops.…”

Si/SiGe ICs for ultra-broadband communications: The analog signal processing perspective

“…Aside from spectral efficiency, bandwidth and noise, hardware complexity and overall power consumption become important issues, considered in current research, e.g. using a Costas loop [3], or demodulation of differential QPSK signals without carrier recovery [4]. Analog channel equalization for 60 GHz, 10 Gb/s QPSK transmission [5] in a 65 nm CMOS mixed-signal IC, consuming only 45 mW, emphasizes the importance of analog signal processing for low-power, ultra-high-speed wireless systems.…”