2022
DOI: 10.1364/oe.464540
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Wafer-level calibration of large-scale integrated optical phased arrays

Abstract: We present the wafer-level characterization of a 256-channel optical phased array operating at 1550 nm, allowing the sequential testing of different OPA circuits without any packaging steps. Using this, we establish that due to random fabrication variations, nominally identical circuits must be individually calibrated. With this constraint in mind, we present methods that significantly reduce the time needed to calibrate each OPA circuit. In particular, we show that for an OPA of this scale, a genetic optimiza… Show more

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Cited by 14 publications
(5 citation statements)
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“…The characterization of the OPA was performed at the wafer-level as described in previous work 38 . This avoids chip dicing as well as complex packaging, which greatly facilitates the evaluation of multiple circuits.…”
Section: Resultsmentioning
confidence: 99%
“…The characterization of the OPA was performed at the wafer-level as described in previous work 38 . This avoids chip dicing as well as complex packaging, which greatly facilitates the evaluation of multiple circuits.…”
Section: Resultsmentioning
confidence: 99%
“…A module combining dedicated photonics and CMOS chips has validated coherent detection of the reflected light with extraction of speed and distance of the illuminated object. Specific test benches have been developed to characterize LiDAR functions at wafer level [2][3][4] and in open space [5]. The experimental results have validated the models.…”
Section: Running Developmentsmentioning
confidence: 98%
“…The characterization of the OPA was performed at the wafer-level as described in previous work [35]. This avoids chip dicing as well as complex packaging which greatly facilitates the evaluation of multiple circuits.…”
Section: D Beam Scanning With Quasi-static Cantilever Operationmentioning
confidence: 99%