2023
DOI: 10.1016/j.engfailanal.2022.106986
|View full text |Cite
|
Sign up to set email alerts
|

Wafer-level chip-scale package lead-free solder fatigue: A critical review

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
4
1

Citation Types

0
6
0

Year Published

2023
2023
2025
2025

Publication Types

Select...
8

Relationship

0
8

Authors

Journals

citations
Cited by 13 publications
(6 citation statements)
references
References 70 publications
0
6
0
Order By: Relevance
“…After the thermomechanical process, the microstructures of the samples were characterized through nanoindentation mapping equipped with a nano-positioning module. It should be noted that the solder bump at the corner site of the assembly, as the most vulnerable part, 33 was considered for this experiment. Nanoindentation testing (NanoTest Vantage) was conducted on a surface at the center of solder bumps with windows of 100 μm × 100 μm by a diamond Berkovich tip.…”
Section: Methodsmentioning
confidence: 99%
“…After the thermomechanical process, the microstructures of the samples were characterized through nanoindentation mapping equipped with a nano-positioning module. It should be noted that the solder bump at the corner site of the assembly, as the most vulnerable part, 33 was considered for this experiment. Nanoindentation testing (NanoTest Vantage) was conducted on a surface at the center of solder bumps with windows of 100 μm × 100 μm by a diamond Berkovich tip.…”
Section: Methodsmentioning
confidence: 99%
“…With the rapid development of microelectronics packaging technology, to improve the integration and reduce the size of devices, the surface mount technology (SMT) assembly, new chip scale packaging (CSP), ball grid array (BGA), and multi-chip module (MCM) packaging technologies are widely used to directly realize the electrical and mechanical connection between different materials through solder joint interconnection, which will inevitably produce stress concentration and dramatically increase its strain level [5]. The coefficient of thermal expansion (CTE) of different materials between layers is different, which will inevitably lead to thermal failure, as shown in Figure 1.…”
Section: Introductionmentioning
confidence: 99%
“…Materials 2024, 17, x FOR PEER REVIEW 2 of 15 (MCM) packaging technologies are widely used to directly realize the electrical and mechanical connection between different materials through solder joint interconnection, which will inevitably produce stress concentration and dramatically increase its strain level [5]. The coefficient of thermal expansion (CTE) of different materials between layers is different, which will inevitably lead to thermal failure, as shown in Figure 1.…”
Section: Introductionmentioning
confidence: 99%
“…Over the past decades, the electronics industry has witnessed a rapid evolution toward smaller and more complex devices, leading to increased demands on the reliability and durability of solder joints (Bani Hani et al, 2023a;Arriola et al, 2022;Samavatian et al, 2020aSamavatian et al, , 2022aXiong et al, 2023). One of the significant challenges faced by electronic instruments is lowcycle fatigue (LCF) in solder joints, which has emerged as a critical failure mechanism (Wei et al, 2023b).…”
Section: Introductionmentioning
confidence: 99%