Wafer-Level Chip-Scale Packaging

Qu, Shichun; Liu, Yong

doi:10.1007/978-1-4939-1556-9

Cited by 15 publications

(3 citation statements)

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“…Wafer-scale fabrication has enabled the repeatable production of biodegradable e-PCBs, which offers more compact and advanced performances via chip-scale integration, and facilitates the assembly of biodegradable chips allowing advanced logical processes. [69,70] Figure 4e demonstrates e-PCB-based disposable Bluetooth device with high electrical performance between biodegradable interconnects and commercial devices on the biodegradable substrate. Printed circuits are composed of Mg (≈500 nm) interconnects that are transferred onto the PBAT (≈100 μm) substrate, and SMDs for the Bluetooth-based UV sensing circuit are electrically connected with an Ag conductive epoxy.…”

Section: Application In Wafer-scale Fabrication and Printed Circuits ...mentioning

confidence: 99%

Ecofriendly Transfer Printing for Biodegradable Electronics Using Adhesion Controllable Self‐Assembled Monolayers

Lee,

Bae

et al. 2023

Adv Funct Materials

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The biodegradable electronics are on the rise, not just due to their role in medical implants, but also because of their eco‐friendly attributes. A variety of methods, including transfer printing, have been employed to integrate inorganic electronics onto biodegradable polymer substrates. However, the use of expensive materials, multiple intermediary steps, and labor‐intensive procedures can undermine their environment‐friendly benefits. Here, a straightforward yet efficient fabrication method is introduced for creating high‐performance biodegradable electronic devices. This method leverages the controlled adhesion between the biodegradable device and substrate using self‐assembled monolayers of octadecyltrichlorosilane. Mechanical and thermal analyses based on scratch tests and time‐domain thermoreflectance quantify the adhesion by adjusting the packing density of octadecyltrichlorosilane. Controlled adhesion allows the photolithography process without delamination while facilitating easy delamination during transfer printing. The authors demonstrate the direct fabrication of electronics consisted of inorganic materials (Mg, Zn, SiO2, Si nanomembrane) on wafers and transfer‐printing onto polymer substrates via a single transfer step. This streamlined approach enables wafer‐scale fabrication of biodegradable electronics, highlighting its potential for mass manufacturing. Pilot conceptual demonstration of mass‐produced edible hydration sensors and their application in salivation measurement through in vivo model show the potential capability of proposed fabrication method in the use of practical level.

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Section: Application In Wafer-scale Fabrication and Printed Circuits ...mentioning

confidence: 99%

Ecofriendly Transfer Printing for Biodegradable Electronics Using Adhesion Controllable Self‐Assembled Monolayers

Lee,

Bae

et al. 2023

Adv Funct Materials

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“…Through-silicon vias (TSVs) in combination with wafer thinning provide electrical connections via the back-side of a die's substrate, enabling stacks of more than two dies. Packaging costs are drastically reduced by using cheaper materials and wafer-level processes [3]. The I/O-to-pin fan-out functionality of package substrates is replaced by redistribution metal layers, cost-effectively manufactured at wafer level.…”

Section: Ieee Std P1838's Flexible Parallel Port and Its Specificatiomentioning

confidence: 99%

IEEE Std P1838's flexible parallel port and its specification with Google's protocol buffers

Liu

Shao

Jiao

et al. 2018

2018 IEEE 23rd European Test Symposium (ETS)

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IEEE Std P1838 is the DfT standard-under-development for 3D test access into dies meant to be used in 3D multi-die stack assemblies. P1838 is the first DfT standard to include a flexible parallel port (FPP): an optional, scalable multi-bit ('parallel') test access mechanism, offering higher test access bandwidth compared to the mandatory one-bit ('serial') port. In this paper, we describe P1838's FPP and propose a formal FPP specification language based on Google's Protocol Buffers (PBs), that potentially could become part of the standard. For a realistic example FPP, we provide its formal specification. Finally, we report on a demonstrator software tool, developed by using PBs-generated data access routines, that converts an FPP specification into a corresponding Verilog netlist. * Yu Li is currently with the ; Ming Shao is currently with Punch Powertrain, ming.shao@punchpowertrain.com; Hailong Jiao is currently also with the Shenzhen Graduate School of Peking University, jiaohl@pkusz.edu.cn. 2018 23rd IEEE European Test Symposium (ETS) !

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“…The full wafer redistribution and printed circuit board embedding described in this paper was carried out using the first generation wafers in 180 nm technology. The applied redistribution layer (RDL) technology was adapted from stateof-the-art processes for fan-in wafer level chip size packaging which are broadly used today [6,7]. The full wafer embedding technology was adapted from a standard technology for chip embedding into printed circuit boards [8].…”

Section: Introductionmentioning

confidence: 99%

Full wafer redistribution and wafer embedding as key technologies for a multi-scale neuromorphic hardware cluster

Zoschke

Güttler

Böttcher

et al. 2017

2017 IEEE 19th Electronics Packaging Technology Conference (EPTC)

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Together with the Kirchhoff-Institute for Physics the Fraunhofer IZM has developed a full wafer redistribution and embedding technology as base for a large-scale neuromorphic hardware system. The paper will give an overview of the neuromorphic computing platform at the Kirchhoff-Institute for Physics and the associated hardware requirements which drove the described technological developments.In the first phase of the project standard redistribution technologies from wafer level packaging were adapted to enable a high density reticle-to-reticle routing on 200 mm CMOS wafers. Neighboring reticles were interconnected across the scribe lines with an 8 µm pitch routing based on semi-additive copper metallization which was photo defined by full field mask aligning equipment. Passivation by photo sensitive benzocyclobutene (BCB) was used to enable a second intra-reticle routing layer. Final IO pads of nickel with flash gold were generated on top of each reticle. For final electrical connection the wafers were placed into mechanical fixtures and the IOs of all reticles were touched by elastomeric connectors. With that concept neuromorphic systems based on full wafers could be assembled and tested. The fabricated high density inter-reticle routing revealed a very high yield of larger than 99.9 %.In order to allow an upscaling of the system size to a large number of wafers with feasible effort a full wafer embedding concept for printed circuit boards was developed and proven in the second phase of the project. The wafers were thinned to 250 µm and laminated with additional prepreg layers and copper foils into a core material. A 200 mm circular cut was done into the core material and the inner prepreg layers to create the required clearance for the wafer. After lamination of the PCB panel the reticle IOs of the embedded wafer were accessed by micro via drilling, copper electroplating, lithography and subtractive etching of the PCB wiring structure.The created wiring with 50 µm line width enabled an access of the reticle IOs on the embedded wafer as well as a board level routing. The panels with the embedded wafers were subsequently stressed with up to 1000 thermal cycles between 0 °C and 100 °C and have shown no severe failure formation over the cycle time.

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Wafer-Level Chip-Scale Packaging

Cited by 15 publications

References 0 publications

Ecofriendly Transfer Printing for Biodegradable Electronics Using Adhesion Controllable Self‐Assembled Monolayers

Ecofriendly Transfer Printing for Biodegradable Electronics Using Adhesion Controllable Self‐Assembled Monolayers

IEEE Std P1838's flexible parallel port and its specification with Google's protocol buffers

Full wafer redistribution and wafer embedding as key technologies for a multi-scale neuromorphic hardware cluster

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