Wafer level integration of an advanced logic-memory system through 2nd generation CoWoS® technology

Chen, W. Chris; Hu, Clark; Ting, Kong; Wei, Vincent; Yu, Tianjun; Huang, Shih-Hian; Chang, Victor C. Y.; Wang, C. T.; Hou, S. Y.; Wu, Cheng‐Hsien; Yu, Douglas

doi:10.23919/vlsit.2017.7998198

Cited by 23 publications

(3 citation statements)

References 1 publication

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“…Meanwhile, 2.5D integration of the processor keeps TSVs out of the large and expensive die of the system, while enabling effective removal of the large amount of heat it generates. Figure 1.37 shows both a conceptual drawing and an optical image of the cross section of an HBM solution from [48]. The optical image illustrates the relative dimensions of the different parts of the memory system.…”

Section: Monolithicmentioning

confidence: 99%

Wireless Interface Technologies for 3D IC and Module Integration

Kuroda

Yip

2021

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Synthesising fifteen years of research, this authoritative text provides a comprehensive treatment of two major technologies for wireless chip and module interface design, covering technology fundamentals, design considerations and tradeoffs, practical implementation considerations, and discussion of practical applications in neural network, reconfigurable processors, and stacked SRAM. It explains the design principles and applications of two near-field wireless interface technologies for 2.5-3D IC and module integration respectively, and describes system-level performance benefits, making this an essential resource for researchers, professional engineers and graduate students performing research in next-generation wireless chip and module interface design.

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Section: Monolithicmentioning

confidence: 99%

Wireless Interface Technologies for 3D IC and Module Integration

Kuroda

Yip

2021

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“…Due to its fine pitch and micro-size characteristics, it is widely used in the packaging and integration of CMOS image sensors, HB LED modules, stacked memories, Logic + MemorySiP, Logic and Analog 3D SOC/Sip, etc. [5][6][7][8]. Taking a typical 2.5 D advanced package as an example, CoWoS (chip on wafer on substrate) is a packaging structure based on a silicon adapter board and TSV technology and launched by TSMC in 2012 [9,10].…”

Section: Introductionmentioning

confidence: 99%

Research on Surface Morphology of Gold Micro Bumps Based on Monte Carlo Method

Tian

Qian

et al. 2023

Micromachines

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In advanced packaging technology, the micro bump has become an important means of chip stacking and wafer interconnection. The reliability of micro bumps, which plays an important role in mechanical support, electrical connection, signal transmission and heat dissipation, determines the quality of chip packaging. Surface morphological defects are one of the main factors affecting the reliability of micro bumps, which are closely related to materials and bonding process parameters. In this paper, the electrodeposition process of preparing gold bumps is simulated at the atomic scale using the Kinetic Monte Carlo method. The differences in surface morphology and roughness of the plated layer are studied from a microscopic perspective under different deposition parameters. The results show that the gold micro bumps prepared by electrodeposition have better surface quality under conditions of lower deposition voltage, lower ion concentration and higher plating temperature, which can provide significant guidance for engineering applications.

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“…Copper pillar bump is widely used in 3D integrated packaging because of their smaller packaging size, excellent electrical and mechanical properties [5][6][7][8]. Currently, the most advanced threedimensional integration technologies, such as HBM [9,10], CoWoS [11,12], Foveros [13,14], etc., use the diameter of copper pillar bumps of about of 20 μm, while in the field of Micro LED, the size of micro-interconnection has reached 10μm or even smaller [15][16][17][18]. This size will continue to shrink in the future.…”

Section: Introductionmentioning

confidence: 99%

Research on Ni3Sn4 intermetallic compound for 5μm diameter Cu/Ni/Sn-3.0Ag micro bumps

Dai

Zhang

Yan

et al. 2022

IEICE Electron. Express

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for 5 μm diameter micro bumps, the interfacial intermetallic compounds (IMCs) seriously affects the interconnection performance of micro bumps. In this paper, we focused on the discussion of the growth and control mechanism of IMCs of 5um diameter micro bumps at different temperatures and durations. The growth mechanism and morphology of Ni3Sn4 IMC was studied. Through the EDS analysis of the cross-sectional micro bumps, it could be determined that the composition of the slender columnar crystal IMC was Ni3Sn4. When the heating temperature was higher than the melting point of Sn-3.0wt%Ag solder, the IMC would exhibit uneven and abnormal growth along the Sn grain boundary. Furthermore, the IMC growth and diffusion mechanisms of solid-solid and solid-liquid interface reaction were discussed respectively. Finally, based on the temperature and duration of the growth and evolution of the Ni3Sn4 IMC, we gave appropriate suggestions for the use of small-sized micro bumps.

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Wafer level integration of an advanced logic-memory system through 2^nd generation CoWoS® technology

Cited by 23 publications

References 1 publication

Wireless Interface Technologies for 3D IC and Module Integration

Wireless Interface Technologies for 3D IC and Module Integration

Research on Surface Morphology of Gold Micro Bumps Based on Monte Carlo Method

Research on Ni<sub>3</sub>Sn<sub>4</sub> intermetallic compound for 5μm diameter Cu/Ni/Sn-3.0Ag micro bumps

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