Wafer-level vacuum/hermetic packaging technologies for MEMS

Wafer-Level Vacuum Packaging Enabled by Plastic Deformation and Low-Temperature Welding of Copper Sealing Rings With a Small Footprint

“…In addition, the Cu ring in the cap substrate maintained an intact line shape after bonding, verifying that no reflow had occurred. The excellent bonding strength in combination with the small sealing ring footprint achieved here enables further miniaturization of vacuum packages compared to alternative metal-based vacuum packaging techniques, which use sealing rings that are typically at least 100 µm wide [13], [14], [16], [18], [22], [23], [25], [33], [36], [37], [39].…”

“…Various metal-based wafer-level hermetic packaging methods have been proposed, including solder bonding [11]- [14], eutectic bonding [15]- [18], solid-liquid inter-diffusion (SLID) bonding [13], [19], [20], surface activated bonding (SAB) [21], and thermo-compression bonding [22]- [27]. All these technologies have individual advantages and disadvantages.…”

“…All these technologies have individual advantages and disadvantages. Drawbacks of solder bonding and eutectic bonding are that the melting of solder metals and alloys can cause reflow problems, and to ensure sufficient hermeticity and bond strength, the sealing ring widths typically are more than 100 µm [13], [14], [16], [18]. For SLID bonding, voids can occur in the intermetallic compound layer, and special care has to be taken in designing the sealing layer thickness and in controlling the temperature ramping during bonding to get uniform and strong bonds [19], [20], [28].…”

Wafer-Level Vacuum Packaging of Smart Sensors

“…In this paper, we review progress in the development of WLVP, discussing techniques that have been reported for the deposition of seals, wafer-to-wafer bonding, and getter deposition and activation, and we compare the different approaches in the context of device requirements. Although a number of comprehensive papers have been published on the related topics of CMOS and MEMS integration [2,3,4,5,6], wafer-level packaging (WLP) of MEMS [5,6,7,8,9,10,11,12], and WLVP of MEMS [10,13,14,15,16], no review has addressed the WLVP of SoC smart sensors. In the cases where topical overlap exists, more recent and/or more detailed information is provided.…”

State-of-the-art MEMS and microsystem tools for brain research

“…MEMS-based solutions for feedthroughs and hermetic capsules reduce the volume of a microsystem by several orders of magnitude compared with conventional titanium housings with ceramic feedthroughs. Furthermore, wafer-level packaging of sensor arrays and vertical enclosures have been demonstrated using a variety of low-temperature eutectic bonds 196 and thus also have the potential to be cost-effective and compatible with many materials.…”