Wafer-scale transferred multilayer MoS₂ for high performance field effect transistors

Abstract

Chemical vapor deposition synthesis of semiconducting transition metal dichalcogenides (TMDs) offers a new route to build next-generation semiconductor devices. But realization of continuous and uniform multilayer (ML) TMD films is still limited by their specific growth kinetics, such as the competition between surface and interfacial energy. In this work, a layer-bylayer vacuum stacking transfer method is applied to obtain uniform and non-destructive ML-MoS 2 films. Back-gated field effect transistor (FET) arrays of 1L-and 2L-MoS 2 are fabricated on the same wafer, and their electrical performances are compared. We observe a significant increase of field-effect mobility for 2L-MoS 2 FETs, up to 32.5 cm 2 V −1 s −1 , which is seven times higher than that of 1L-MoS 2 (4.5 cm 2 V −1 s −1 ). Then we also fabricated 1L-, 2L-, 3L-, and 4L-MoS 2 FETs to further investigate the thickness-dependent characteristics of transferred ML-MoS 2 . Measurement results show a higher mobility but a smaller current on/off ratio as the layer number increases, suggesting that a balance between mobility and current on/ off ratio can be achieved in 2L-and 3L-MoS 2 FETs. Dual-gated structure is also investigated to demonstrate an improved electrostatic control of the ML-MoS 2 channel.

An Artificial Neutral Network Chip Based on Two-Dimensional Semiconductor

“…While wafer-scale 2DLM synthesis by CVD has been recently demonstrated 5,6,64 , other challenges impede practical application, including processing of electrical contacts and dielectric layer deposition due to atomic thickness and complex interface conditions. Here, based on the high quality continuous MoS2 film we previously reported [65][66][67] (Fig. 3b, also see Moreover, the implementation of high-performance analog circuits requires device modeling with higher accuracy [72][73][74] .…”

Realizing Wafer‐Scale and Low‐Voltage Operation MoS2 Transistors via Electrolyte Gating

“…The width and length of the channel are 100 and 50 µm, respectively. We also transfer MoS 2 film onto polyimide (PI) substrate [46] and fabricate an electrolyte-gated MoS 2 transistor array. The fabrication process is shown in Figure S4, Supporting Information, and the transistor characteristic is displayed in Figure S5, Supporting Information.…”

Recent progress in devices and circuits based on wafer-scale transition metal dichalcogenides

“…The CMOS inverter, consisting of both NMOS and PMOS, is widely used because it has the advantages of large noise margin and small static power consumption. To form a CMOS inverter based on 2DLMs FETs, transfer method is used to integrate p-type material and n-type channel to make up on the same substrate [99]. As shown in Figure 3(d (Figure 3(e)).…”