Warpage and Oxide Precipitate Distributions in CZ Silicon Wafers

Abstract

Several types of as-received and complementary metal oxide semiconductor (CMOS) thermal simulated 100 mm wafers were used for warpage study under different annealing conditions. The results indicated that as-received wafers showed little increase in warpage up to 1000~ furnace temperature and 61.0 cm/min insertion rate. For the CMOS thermal simulation processed wafers, both the prior amount of oxygen precipitation, A[O~], where A[O~] is the decrease in interstitial oxygen concentration, and bulk microdefect morphology affected warpage. For A[O,] less than ca. 26 ppma, wafers with predominantly octahedral precipitates without associated dislocations plus a low density of small plate-type and dot-like precipitates underwent much less warpage than wafers with predominantly large octahedral precipitates and precipitatedislocation-complexes (PDCs). When the h[Oi] was higher than 26 ppma, the defects consisted of a high density of large octahedral-shaped precipitates and PDCs and thus warpage became inevitable.

Phosphorus Concentration Limitation in Czochralski Silicon Crystals

“…This is similar to wafer warpage caused by dislocation generation from precipitate dislocation complexes (PDC) under high thermal stresses. [44][45][46] Conclusion The maximum phosphorus concentration that can be incorporated in a silicon crystal using the Czochralski crystal growth method was investigated. The value was found to be related to the hot-zone configuration and is about 1.11 ϫ 10 20 atom/cm 3 for 100 mm (111) crystals grown from a short tank grower with an 18 kg charge size.…”

In Situ Rapid Thermal Oxidation and Reduction of Copper Thin Films and Their Applications in Ultralarge Scale Integration

“…Compared to Al ͑2.7 ⍀ cm͒ and Al alloys ͑Ͼ4.0 ⍀ cm͒, Cu has a number of benefits, such as lower bulk resistivity ͑1.7 ⍀ cm͒, higher electromigration resistance, 1 higher melting point ͑1085°C for Cu vs. 660°C for Al͒, and lower reactivity with commonly used diffusion barrier materials. 2 As a potential candidate for ULSI interconnect applications, copper thin films may be deposited by physical vapor deposition ͑PVD͒, 3 chemical vapor deposition ͑CVD͒, 4 electroless plating, 5 and electrochemical deposition ͑ECD͒. 6 One of the disadvantages of copper is that it is readily oxidized in air or in a humid ambient at low temperature.…”

Chemical Wet Etching of Silicon Wafers from a Mixture of Concentrated Acids

“…(WCE) is a simple method which can be performed on the wafers to reduce the surface roughness from the BG process. Among the chemicals which have been long used in the WCE process are KOH, Hydrofluoric acid (HF), Tetramethyl Ammonium Hydroxide (TMAH) and Ethylene Diamine Pyrocatechol (EDP), but improvements have been made in the chemical compositions and conditions of the WCE [10,11,13].…”