Warped-DMR: Light-weight Error Detection for GPGPU

Jeon, Hyeran; Annavaram, Murali

doi:10.1109/micro.2012.13

Cited by 62 publications

(37 citation statements)

References 12 publications

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“…Techniques such as redundant multi-threading can detect most multi-bit faults (e.g., [19] [43]). Many error correcting codes (e.g., DEC-TED ECCs) can detect and correct multi-bit faults, and cyclic redundancy codes (CRCs) can provide robust multibit error detection [22].…”

Section: Existing Multi-bit Remediation Techniquesmentioning

confidence: 99%

Calculating Architectural Vulnerability Factors for Spatial Multi-Bit Transient Faults

Wilkening

Sridharan

et al. 2014

2014 47th Annual IEEE/ACM International Symposium on Microarchitecture

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Abstract-Reliability is an important design constraint in modern microprocessors, and one of the fundamental reliability challenges is combating the effects of transient faults. This requires extensive analysis, including significant fault modeling to allow architects to make informed reliability tradeoffs. Recent data shows that multi-bit transient faults are becoming more common, increasing from 0.5% of SRAM faults in 180nm to 3.9% in 22nm, and are predicted to be even more prevalent in smaller technology nodes. Therefore, accurately modeling the effects of multi-bit transient faults is increasingly important to the microprocessor design process.Architecture vulnerability factor (AVF) analysis is a method to model the effects of single-bit transient faults. In this paper, we propose a method to calculate AVFs for spatial multi-bit transient faults (MB-AVFs) and provide insights that can help reduce the impact of these faults. First, we describe a novel multi-bit AVF analysis approach for detected, uncorrected errors (DUEs) and show how to measure DUE MB-AVFs in a performance simulator. We then extend our approach to measure SDC MB-AVFs. We find that MB-AVFs are not derivable from single-bit AVFs. We also find that larger fault modes have higher MB-AVFs. Finally, we present a case study on using MB-AVF analysis to optimize processor design, yielding SDC reductions of 86% in a GPU vector register file.

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Section: Existing Multi-bit Remediation Techniquesmentioning

confidence: 99%

Calculating Architectural Vulnerability Factors for Spatial Multi-Bit Transient Faults

Wilkening

Sridharan

et al. 2014

2014 47th Annual IEEE/ACM International Symposium on Microarchitecture

View full text Add to dashboard Cite

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“…However, the utilization of many-core system is low, especially the many-core system based on GPU. Usually, 7%-77% hardware resources are idle in many-core system [19].…”

Section: Background and Related Workmentioning

confidence: 99%

“…Jeon [19] exploited idle threads and execution unit in GPGPU for reliability. Rather regular idle core in a SM of GPU, DVR exploit idle slice in many-core architecture, a more general idle using.…”

Section: Background and Related Workmentioning

confidence: 99%

“…For low performance overhead if the application requires low reliability, design concept of DVR is not to optimize system for fault-tolerant but to avoid modification to existing highly- Works on-demand dynamically idle redundancy coupling exploiting DVR(this paper) yes yes yes Relax [5] yes no no DCC [9],Joseph [15], no yes no smart-core [16] warped-DMR [19] no no yes optimized micro-architectures. It employs selectively redundancy scope for the different reliability requirements among vary applications.…”

Section: Background and Related Workmentioning

confidence: 99%

“…As a result, usually the utilization of many-core system is low, and there are many idle resources. Jeon [19] implements DMR using idle threads in GPGPU. We also consider using idle core for redundant execution in many-core system.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Device View Redundancy: An Adaptive Low-Overhead Fault Tolerance Mechanism for Many-Core System

Jia

Zhang

2013

2013 IEEE 10th International Conference on High Performance Computing and Communications &Amp; 2013 IEEE International Conferen

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Continued increasing of fault rate in integrate circuit makes processors more susceptible to errors, especially many-core processor. Meanwhile, most systems or applications do not need full fault coverage, which has excessive overhead. So on-demand fault tolerance is desired for these applications. In this paper, we propose an adaptive low-overhead fault tolerance mechanism for many-core system, called Device View Redundancy (DVR). It treats fault tolerance as a device that can be configured and used by application when high reliability is needed. Nevertheless, DVR exploits the idle resources for lowoverhead fault tolerance, which is based on the observation that the utilization of many-core system is low due to lack of parallelism in application. Finally, the experiment shows that the performance overhead of DVR is reduced by 16%to 98% compared with full Dual Modular Redundancy (DMR).

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Evaluating the Viability of Application-Driven Cooperative CPU/GPU Fault Detection

Liu

Lee

Vetter

2014

Euro-Par 2013: Parallel Processing Workshops

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Warped-DMR: Light-weight Error Detection for GPGPU

Cited by 62 publications

References 12 publications

Calculating Architectural Vulnerability Factors for Spatial Multi-Bit Transient Faults

Calculating Architectural Vulnerability Factors for Spatial Multi-Bit Transient Faults

Device View Redundancy: An Adaptive Low-Overhead Fault Tolerance Mechanism for Many-Core System

Evaluating the Viability of Application-Driven Cooperative CPU/GPU Fault Detection

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