WASP: A WSI Associative String Processor

Seventh IEEE International Conference on Wafer Scale Integration

“…Applications include image analysis, video processing, and 3D image generation [ll]. The project team has manufactured three demonstration devices (WASP 2a,2b,and 3), and is under contract to demonstrate a working WASP system in 1996. The purpose of this study is to analyze the hypothetical architecture described in [12], and to report the expected yield and reliability results.…”

“…An low density interconnect (LDI) substrate supports the main WASP wafer and provides intermediate wiring pads. An high density interconnect (HDI) wafer, attached on top of the WASP wafer, is used for signal and power distribution, with interconnections made using Hughes Aircraft Corporation indium bump technology [3]. A similar arrangement is assumed for the hypothetical device.…”

“…Complex WSI devices require detailed mathematical modeling and a systems engineering approach to achieve commercial success. This paper describes a combined yield, reliability, testing and reconfiguration model for the WASP device [3]. A yieldreliability analysis is presented for a hypothetical WASP device based on an extrapolation of the existing WASP 2a [4], WASP 2b [5], and WASP 3 [3] devices.…”

Defect and fault tolerant interconnection strategies for WASP devices

“…This paper was presented at the IEEE Intemational Conference on Wafer Scale Integration, San Francisco, CA, January 18- 20, 1995. M. Hussaini and R. Lea [3]), have shown the occurrences of interconnect defects of varying sizes on WASP bus structures [13], [14]. Figs.…”

An Implementation Of A Set Mode For Prolog On A Parallell Associative Processor

“…Although the above data specifies the TRAX machine, the number of APEs will increase in the future. Harbiger [9] describes wafer scale multichip modules of APES; and Lea [8] describes large monolithic wafers. These implementations of the ASP will increase the storage capacity of ASP based machines to O( IO6) APEs.…”