WCET Analysis of Multi-level Non-inclusive Set-Associative Instruction Caches

Hardy, Damien; Puaut, Isabelle

doi:10.1109/rtss.2008.10

Cited by 82 publications

(115 citation statements)

References 21 publications

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“…For example, if we treat every possible access at a level as always happening, the analysis may become unsafe, since doing so may underestimate the set reuse distances 1 of memory blocks [8].…”

Section: Problem Statementmentioning

confidence: 99%

“…For a reference at a cache level, a cache access classification (CAC) can be used to represent whether the cache access at this level will occur: always (A) denotes the access will always occur, never (N) denotes the access will never happen, and uncertain (U) denotes the access may occur [8]. In order to ensure safety, the updates of the abstract cache states due to U accesses need to take into account the two possible cases (access occurring and not occurring).…”

Section: Problem Statementmentioning

confidence: 99%

“…Recently, multi-level cache analysis has drawn much attention in real-time systems [8,12,4,18,9], since there is a rising need of exploiting the high-performance processors, which are often equipped with multi-level caches. However, compared to single-level cache analysis, multi-level cache analysis is much more challenging.…”

Section: Introductionmentioning

confidence: 99%

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Top-down and bottom-up multi-level cache analysis for WCET estimation

Zhang

Koutsoukos

2015

21st IEEE Real-Time and Embedded Technology and Applications Symposium

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Abstract-In many multi-core architectures, inclusive shared caches are used to reduce cache coherence complexity. However, the enforcement of the inclusion property can cause invalidation of memory blocks at higher cache levels. In order to ensure safety, analysis of cache hierarchies with inclusive caches for worst-case execution time (WCET) estimation is typically based on conservative decisions. Thus, the estimation may not be tight. In order to tighten the estimation, this paper proposes an approach that can more precisely analyze the behavior of a cache hierarchy maintaining the inclusion property. We illustrate the approach in the context of multi-level instruction caches. The approach first analyzes all the inclusive caches in the hierarchy in a bottom-up direction, and then analyzes the remaining non-inclusive caches in a top-down direction. In order to capture the inclusion victims and their effects, we also propose a concept of aging barrier and integrate it with the traditional must and persistence analyses to safely slow down their aging process so as to derive more precise analyses. We evaluate the proposed approach on a set of benchmarks and the evaluation reveals that the estimations are tightened.

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Section: Problem Statementmentioning

confidence: 99%

Section: Problem Statementmentioning

confidence: 99%

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Top-down and bottom-up multi-level cache analysis for WCET estimation

Zhang

Koutsoukos

2015

21st IEEE Real-Time and Embedded Technology and Applications Symposium

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“…1 Memory accesses from the data and instruction caches of a single CPU were multiplexed over a single connection to the local interconnect of the tile. All these choices are known to complicate timing analysis and/or to reduce the precision of the analysis [34], [35], and thus we revert to more conservative choices: We use the LRU replacement policy, a fully write-through policy, and we let the instruction and data caches access the local tile interconnect through separate connexions. Note that the use of a write-through policy reduces the processing speed of each CPU.…”

Section: B Modifications Of the Tile Structurementioning

confidence: 99%

Reconciling performance and predictability on a many-core through off-line mapping

Carle

Djemal

Genius

et al. 2014

2014 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)

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Abstract-We start from a general-purpose many-core architecture designed for average-case performance and ease of use. In particular, its distributed shared memory programming model allows the use of a code generation flow based on the (unmodified) gcc compiler chain. We modify this architecture and extend the code generation flow to allow the construction of efficient hard real-time systems starting from dependent task specifications. We rely on a static (off-line) real-time scheduling paradigm welladapted to embedded control and signal processing applications with regular control structure.We modify the architecture (and in particular the on-chip network) to allow the implementation of static schedules with very high (clock cycle) temporal precision. On the software side, we define application mapping rules ensuring that the timing precision provided by the hardware is not lost. These mapping rules include requirements on the allocation of data variables to specific RAM banks and on the use of locks to ensure the absence of contentions during access to shared resources. Applications complying with these rules can be written manually or automatically obtained using a new mapping tool that takes all the allocation and scheduling decisions. Compilation of the resulting C code is still done using the (unmodified) gcc compiler chain. The resulting platform provides good performance, and at the same provides very high timing precision, as shown by two case studies (an embedded controller and an implementation of the FFT).We conclude our paper with a presentation of some ongoing work on the subject: A case study (an implementation of the H.264 decoder) meant to test the limitations of our method.

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“…There have been many studies on WCET analysis, and most efforts have focused on analyzing the WCET for single-core processors [Healy et al 1995;Stappert et al 2001;Li and Malik 1995;Li et al 1996;Ottosson and Sjodin 1997;Puschner and Burns 2000;Hardy 2008;White et al 1997;Ramaprasad and Mueller 2005;Lundqvist and Stenstrom 1999a;Staschulat and Ernst 2006]. A good survey of WCET analysis can be found in [Wilhelm et al 2008].…”

Section: Introductionmentioning

confidence: 99%

Bounding Worst-Case Performance for Multi-Core Processors with Shared L2 Instruction Caches

Yan¹,

Zhang²

2011

Journal of Computing Science and Engineering

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As the first step toward real-time multi-core computing, this paper presents a novel approach to bounding the worst-case performance for threads running on multi-core processors with shared L2 instruction caches. The idea of our approach is to compute the worst-case instruction access interferences between different threads based on the program control flow information of each thread, which can be statically analyzed. Our experiments indicate that the proposed approach can reasonably estimate the worst-case shared L2 instruction cache misses by considering the inter-thread instruction conflicts. Also, the worst-case execution time (WCET) of applications running on multi-core processors estimated by our approach is much better than the estimation by simply assuming all L2 instruction accesses are misses.

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WCET Analysis of Multi-level Non-inclusive Set-Associative Instruction Caches

Abstract: Abstract

Cited by 82 publications

References 21 publications

Top-down and bottom-up multi-level cache analysis for WCET estimation

Top-down and bottom-up multi-level cache analysis for WCET estimation

Reconciling performance and predictability on a many-core through off-line mapping

Bounding Worst-Case Performance for Multi-Core Processors with Shared L2 Instruction Caches

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