Wear out effects in ESD characterization and testing

Smedes, T.; Abessolo-Bidzo, Dolphin

doi:10.1109/eosesd.2015.7314783

Cited by 4 publications

(1 citation statement)

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“…Although the impact of multiple ESD events on metal has been roughly verified, limitations in simulation software make it challenging to accurately determine the ESD robustness of metal. [29][30][31] Even most of the process factories only provide maximum current under DC conditions. As a result, the layout of ESD protection circuits has often relied on experience or information from previous literature.…”

Section: Introductionmentioning

confidence: 99%

Characterization of ESD-induced electromigration on CMOS metallization in on-chip ESD protection circuit

Hou,

Lin

2024

Jpn. J. Appl. Phys.

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Electrostatic Discharge (ESD) and electromigration are critical issues that significantly impact the reliability of integrated circuits (ICs). While both of these phenomena have been studied independently, the combination of the two, ESD-induced electromigration, has received less attention. This work analyzes various types of metal with different lengths, widths, and angles commonly used in ESD protection circuits in the CMOS process. The objective is to observe their behavior under continuous ESD zapping. The ESD-induced electromigration of metallization in the CMOS process has been analyzed, and metal sensitivity to system-level ESD events has also been identified. It is also analyzed from the perspective of energy that the ESD energy that metal can withstand will decrease as the ESD voltage increases, which will be even more detrimental to the ESD reliability of ICs. The findings from this study aim to provide valuable insights for designing metal lines in ICs to enhance ESD protection.

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Section: Introductionmentioning

confidence: 99%