Wet cleaning process for high-yield via-last TSV formation

Watanabe, Naoya; Shimamoto, H.; Kikuchi, Katsuya; Aoyagi, Masahiro; Kikuchi, Hidekazu; Yanagisawa, Azusa; Nakamura, Akio

doi:10.1109/3dic.2016.7970026

Cited by 5 publications

(3 citation statements)

References 4 publications

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“…To overcome these problems, we proposed a novel via-last TSV process using notchless Si etching and wet cleaning of the first metal layer. [15][16][17] In this process, the notching was suppressed by optimizing the deep Si etching conditions. In addition, wet cleaning of the first metal layer was performed with an organic alkaline solution to remove the contaminants and create good electrical contact between the TSV and first metal layer.…”

Section: Introductionmentioning

confidence: 99%

Fabrication and stacking of through-silicon-via array chip formed by notchless Si etching and wet cleaning of first metal layer

Watanabe

Kikuchi²,

Yanagisawa³

et al. 2019

Jpn. J. Appl. Phys.

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We combined a "via-last through-silicon via (TSV) process consisting of notchless Si etching and wet cleaning of the first metal layer" with the solder bonding process using Ar fast atom beam (FAB), and realized the fabrication and three-dimensional (3D) stacking of a high-density TSV array chip. The size of the TSV array was 76 × 500. The diameter and length of the TSV were 6 and 21-22 μm, respectively. As the TSV array chip was very thin (approximately 26 μm) and had a strip-like shape, it was fragile and warped by approximately 90 μm. Hence, an electrostatic chuck was introduced and the TSV array chip was stacked by using a soft material (Cu-Ni-Sn based solder) as a bump and performing low-pressing-load low-temperature bonding with Ar FAB. As a result, the warpage of TSV array chip was suppressed and the TSV array chip was stacked without causing damage to the TSV and Si region. In addition, it was confirmed that the (i) leakage current between TSV-bump pairs is small, (ii) multilayer wiring + TSV + bump connection exhibit low resistance, and (iii) daisy chain is perfectly connected to up to 38 000 TSVs. These results are due to the effects of notchless Si etching, wet cleaning of the first metal layer, introduction of an electrostatic chuck, low-pressing-load low-temperature bonding with a soft material, and Ar FAB. This process will facilitate the development of face-up type 3D stacked sensor systems.

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Section: Introductionmentioning

confidence: 99%

Fabrication and stacking of through-silicon-via array chip formed by notchless Si etching and wet cleaning of first metal layer

Watanabe

Kikuchi²,

Yanagisawa³

et al. 2019

Jpn. J. Appl. Phys.

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“…To overcome these problems and increase the TSV yield, we previously proposed a via-last TSV process using notchless Si etching and wet cleaning of the first metal layer. 19,20) In this process, the notching was suppressed by optimizing the deep Si etching conditions. In addition, wet cleaning of the first metal layer was performed to remove the reaction products on the first metal layer and create good electrical contact between the TSVs and the first metal layer.…”

Section: Introductionmentioning

confidence: 99%

Development of a high-yield via-last through silicon via process using notchless silicon etching and wet cleaning of the first metal layer

Watanabe

Kikuchi²,

Yanagisawa³

et al. 2017

Jpn. J. Appl. Phys.

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A high-yield via-last through silicon via (TSV) process has been developed using notchless Si etching and wet cleaning of the first metal layer. In this process, the notching was suppressed by optimizing the deep Si etching conditions and wet cleaning was performed using an organic alkaline solution to remove reaction products generated by the etchback step on the first metal layer. By this process, a number of small TSVs (TSV diameter: 6 µm; TSV depth: 22 µm; number of TSVs: 20,000/chip) could be formed uniformly on an 8-in. wafer. The electrical characteristics of small TSVs formed by this via-last TSV process were investigated. The TSV resistance determined by four-terminal measurements was approximately 24 mΩ. The leakage current between the TSV and the Si substrate was 2.5 pA at 5 V. The TSV capacitance determined using an inductance–capacitance–resistance (LCR) meter was 54 fF, while the TSV yield determined from TSV chain measurements was high (83%) over an 8-in. wafer.

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“…Moreover, the TSV manufacturing costs for 3D integration is high due to limited yield rate. For example, an 83% yield rate with state-of-the-art manufacturing for an 8-inch wafer is considered as the bestachieved rate for TSV-based ICs (Lau 2010;Watanabe et al 2016Watanabe et al , 2017. On the other hand, the direct wafer-bonding technique in M3D does not face such difficulties, and hence, achieves high yield and low cost (Batude et al 2012;Uhrmann et al 2014).…”

mentioning

confidence: 99%

Performance and Thermal Tradeoffs for Energy-Efficient Monolithic 3D Network-on-Chip

Das

Doppa

Pande

et al. 2018

ACM Trans. Des. Autom. Electron. Syst.

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Three-dimensional (3D) integration enables the design of high-performance and energy-efficient network on chip (NoC) architectures as communication backbones for manycore chips. To exploit the benefits of the vertical dimension of 3D integration, through-silicon-via (TSV) has been predominantly used in state-of-the-art manycore chip design. However, for TSV-based systems, high power density and the resultant thermal hotspot remain major concerns from the perspectives of chip functionality and overall reliability. The power consumption and thermal profiles of 3D NoCs can be improved by incorporating a Voltage-Frequency-Island (VFI)-based power management strategy. However, due to inherent thermal constraints of a TSV-based 3D system, we are unable to fully exploit the benefits offered by the power management methodology. In this context, emergence of monolithic 3D (M3D) integration has opened up new possibility of designing ultra-low-power and high-performance circuits and systems. The smaller dimensions of the inter-layer dielectric (ILD) and monolithic inter-tier vias (MIVs) offer high-density integration, flexibility of partitioning logic blocks across multiple tiers, and significant reduction of total wire-length. In this work, we present the first-ever study of the performance-thermal tradeoffs for energy efficient monolithic 3D manycore chips. In particular, we present a comparative performance evaluation of M3D NoCs with respect to their conventional TSV-based counterparts. We demonstrate that the proposed M3D-based NoC architecture incorporating VFI-based power management achieves a maximum of 29.4% lower energy-delay-product (EDP) compared to the TSV-based designs for a large set of benchmarks. We also demonstrate that the M3D-based NoC shows up to 29.1% lower maximum temperature than the TSV-based counterpart for these benchmarks.

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Wet cleaning process for high-yield via-last TSV formation

Cited by 5 publications

References 4 publications

Fabrication and stacking of through-silicon-via array chip formed by notchless Si etching and wet cleaning of first metal layer

Fabrication and stacking of through-silicon-via array chip formed by notchless Si etching and wet cleaning of first metal layer

Development of a high-yield via-last through silicon via process using notchless silicon etching and wet cleaning of the first metal layer

Performance and Thermal Tradeoffs for Energy-Efficient Monolithic 3D Network-on-Chip

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