WiCkeD: analog circuit synthesis incorporating mismatch

Antreich, K.J.; Eckmueller, J.; Graeb, Helmut; Pronath, M.; Schenkel, F.; Schwencker, R.; Zizala, S.

doi:10.1109/cicc.2000.852720

Cited by 55 publications

(21 citation statements)

References 21 publications

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“…The algorithm then repeats with further sensitivity analyses. "Favorable" can be 1) maximum worst-case distance from the center of the probability density function (pdf) to the closest feasibility boundary [25] or 2) maximum yield [7], [23], i.e., maximum volume under the pdf that is in the polytope feasible region.…”

Section: Design Centering In Feasibility Regionmentioning

confidence: 99%

Globally Reliable Variation-Aware Sizing of Analog Integrated Circuits via Response Surfaces and Structural Homotopy

McConaghy

Gielen

2009

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-This paper presents SANGRIA, a tool for automated globally reliable variation-aware sizing of analog integrated circuits. Its keys to efficient search are adaptive response surface modeling, and a new concept, structural homotopy. Structural homotopy embeds homotopy-style objective function tightening into the search state's structure, not dynamics. Searches at several different levels are conducted simultaneously: The loosest level does nominal dc simulation, and tighter levels add more analyses and {process, environmental} corners. New randomly generated designs are continually fed into the lowest (cheapest) level, always trying new regions to avoid premature convergence. For further efficiency, SANGRIA adaptively constructs response surface models, from which new candidate designs are optimally chosen according to both yield optimality on model and model prediction uncertainty. The stochastic gradient boosting models support arbitrary nonlinearities, and have linear scaling with input dimension and sample size. SANGRIA uses SPICE in the loop, supports accurate/complex statistical SPICE models, and does not make assumptions about the convexity or differentiability of the objective function. SANGRIA is demonstrated on four different analog circuits having from 10 to 50 devices and up to 444 design/process/environmental variables.

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Section: Design Centering In Feasibility Regionmentioning

confidence: 99%

Globally Reliable Variation-Aware Sizing of Analog Integrated Circuits via Response Surfaces and Structural Homotopy

McConaghy

Gielen

2009

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…Other work in synthesizing analog circuits has focused on transistor level techniques to help hardware designers create specialized logic circuits [3,16,22]. Researchers have also leveraged analog accelerators such as neural network accelerators to approximate digital subcomputations written in imperative languages [14,31].…”

Section: Related Workmentioning

confidence: 99%

“…In recent years, there have been advances in compiler techniques that target reconfigurable analog devices devices [2,3,16,22]. The Arco compiler, for example, takes as input a specification of a reconfigurable analog device and a specification of a dynamical system and produces an analog device configuration that simulates the dynamical system [2].…”

Section: Introductionmentioning

confidence: 99%

Time Dilation and Contraction for Programmable Analog Devices with Jaunt

Achour

Rinard

2018

Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Syste

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Programmable analog devices are a powerful new computing substrate that are especially appropriate for performing computationally intensive simulations of neuromorphic and cytomorphic models. Current state of the art techniques for configuring analog devices to simulate dynamical systems do not consider the current and voltage operating ranges of analog device components or the sampling limitations of the digital interface of the device.We present Jaunt, a new solver that scales the values that configure the analog device to ensure the resulting analog computation executes within the operating constraints of the device, preserves the recoverable dynamics of the original simulation, and executes slowly enough to observe these dynamics at the sampled digital outputs. Our results show that, on a set of benchmark biological simulations, 1) unscaled configurations produce incorrect simulations because they violate the operating ranges of the device and 2) Jaunt delivers scaled configurations that respect the operating ranges to produce correct simulations with observable dynamics.

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“…The transistor degradation as well as the degraded circuit netlist at time t are produced, ready for SPICE simulation to get a degraded performance. For design centering/yield optimization, we exemplarily use the design optimization software WiCkeD (Antreich et al, 2000). Its yield analysis and optimization algorithms are based on worst-case distances mentioned above.…”

Section: Softwarementioning

confidence: 99%

“…The proposed lifetime yield optimization flow uses a tool WiCkeD (Antreich et al, 2000) and aging simulator RelXpert from Cadence with NBTI and HCI degradation engines. The lifetime yield of the analog circuit is optimized by maximizing both the fresh worst-case distance and lifetime worst-case distance values, considering the sizing constraints for both fresh and degraded circuits.…”

Section: New Design Flowmentioning

confidence: 99%