Wideband flexible-reach techniques for a 0.5&amp;#x2013;16.3Gb/s fully-adaptive transceiver in 20nm CMOS

Savoj, Jafar; Aslanzadeh, H.A.; Carey, Declan; Erett, Marc; Fang, Wayne; Frans, Yohan; Hsieh, Kenny; Im, Jungho; Jose, Anup; Turker, Didem; Upadhyaya, Parag; Wu, Daniel; Chang, Ken

doi:10.1109/cicc.2014.6945980

Cited by 6 publications

(9 citation statements)

References 4 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…4. The forward path is constituted by Q1, Q2 and load resistance RL1, RL2, and the feedback loop is composed of Q3~Q6 and low-pass filters consisted of Cfb and Rfb [17,28]. Fig.5 (a) and (b) display the output eye diagrams of linear equalizer without middle frequency compensation and with middle frequency compensation respectively.…”

Section: Middle Frequency Amplifiermentioning

confidence: 99%

“…Because of temperature variation, material properties, length and bends, it is very important for equalizer to automatically detect and critically compensate for the high frequency loss of channel. Continuous time adaptive equalizer can adapt its response to both the possible variations of the characteristics of the backplane [15,16,17,18,19]. Ref.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A 36 Gb/s wireline receiver with adaptive CTLE and 1-tap speculative DFE in 0.13 µm BiCMOS technology

Zhang

Yang

2020

IEICE Electron. Express

View full text Add to dashboard Cite

This paper presents a 36 Gb/s receiver equalizer including an adaptive continuous time linear equalizer (CTLE), which is based on slope detection and a half-rate speculative decision feedback equalizer (DFE) in 0.13 µm BiCMOS technology for high speed serial link. The CTLE with middle frequency compensation can not only adjust the ratio of high frequency and low frequency components adaptively, but also provide a small amount of equalization to middle frequency range. A half-rate speculative DFE, which is connected to the back of the CTLE, can satisfy the time constraints and eliminate the residual intersymbol interference. The chip area including pads is about 1.2 mm 2 and the power consumption is about 750 mW under 3.3 V power supply. Measurement results show that the receiver chip can effectively equalize 24 dB loss at Nyquist frequency and a clear eye diagram can be captured at 36 Gb/s.

show abstract

Section: Middle Frequency Amplifiermentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A 36 Gb/s wireline receiver with adaptive CTLE and 1-tap speculative DFE in 0.13 µm BiCMOS technology

Zhang

Yang

2020

IEICE Electron. Express

View full text Add to dashboard Cite

show abstract

“…With proper design techniques, the transceiver in 20nm operates up to 16.3Gb/s. Figure 10(a) shows the 28dB channel used for the testing for 20nm transceiver [1]. The resulting transmitter random jitter (RJ) is 313fs, shown in Figure 10(b).…”

Section: Transceiver Circuitsmentioning

confidence: 99%

“…The robust performance validates all the circuit techniques used for the advanced process nodes. Figure 10: (a) channel loss (S21) for 28dB channel (including test cables) (b) TX output waveform (c) 16.3Gb/s Receiver Eyescan (d) 16.3Gb/s BER for 28dB channel [1] …”

Section: Transceiver Circuitsmentioning

confidence: 99%

See 1 more Smart Citation

Device aware high-speed transceiver design in planar and FinFet technologies

Chang

Savoj

Upadhyaya

et al. 2014

2014 IEEE International Electron Devices Meeting

Self Cite

View full text Add to dashboard Cite

This paper studies the interaction between devices in advanced CMOS processes and the analog circuits used in high-speed transceivers. It describes the impact of variation on the design with both active and passive devices, and devises circuit techniques to mitigate their impact on the performance of transceivers. A case study of transceiver components in 20nm planar and 16nm FinFET processes are used to illustrate the interactions. With proper design techniques, the transceiver in 20nm operates up to 16.3Gb/s and achieves measured bit error rate lower than 10 -15 over 28dB channels.

show abstract

An 11.05 mW/Gbps Quad-Channel 1.25-10.3125 Gbps Serial Transceiver With a 2-Tap Adaptive DFE and a 3-Tap Transmit FFE in 40 nm CMOS

Chen

Wang

et al. 2021

IEEE Access

View full text Add to dashboard Cite

This paper presents a quad-channel 1.25-10.3125 Gbps wireline transceiver implemented in 40 nm CMOS technology. The transmitter consists of a bit width adjustment, a 40:2 multiplexer, a 2:1multiplexer, and a current-mode logic driver with a 3-tap feedforward equalizer. The receiver has a twostage continuous-time linear equalizer, a 2-tap half-rate fully adaptive decision-feedback equalizer, a phase interpolation-based digital clock and data recovery (CDR) followed by a 2:40 demultiplexer, a bit width adaption. The transceiver also supports AC/DC coupling, CDR locking detection, PLL locking detection, loss of signal detection, automatic termination impedance calibration. A ring VCO-based PLL is designed in each lane to save power consumption, and a dual-core LC VCO-based PLL is implemented in each bank to generate a low jitter clock signal. At 10.3125 Gbps, the transceiver can equalize 28 dB Nyquist loss at a bit error rate of 10 −12 , and it consumes 114 mW with a 1.1 V supply. This work presents a high power efficiency of 11.05 mW/Gbps, and the transceiver is suitable for multi-standard applications due to its flexibility and power efficiency.INDEX TERMS Transceiver, feedforward equalizer, continuous-time linear equalizer (CTLE), adaptive decision-feedback equalizer (DFE), clock and data recovery (CDR).

show abstract

Wideband flexible-reach techniques for a 0.5–16.3Gb/s fully-adaptive transceiver in 20nm CMOS

Cited by 6 publications

References 4 publications

A 36 Gb/s wireline receiver with adaptive CTLE and 1-tap speculative DFE in 0.13 µm BiCMOS technology

A 36 Gb/s wireline receiver with adaptive CTLE and 1-tap speculative DFE in 0.13 µm BiCMOS technology

Device aware high-speed transceiver design in planar and FinFet technologies

An 11.05 mW/Gbps Quad-Channel 1.25-10.3125 Gbps Serial Transceiver With a 2-Tap Adaptive DFE and a 3-Tap Transmit FFE in 40 nm CMOS

Contact Info

Product

Resources

About