Width Effect on Hot-Carrier-Induced Degradation for 90 nm Partially Depleted SOI CMOSFETs

Abstract

The hot-carrier-induced degradation of partially depleted silicon-on-insulator complementary metal-oxide-semiconductor field-effect transistors (CMOSFETs) at various applied voltages was investigated using 90 nm body-contact silicon-on-insulator (BC-SOI) devices with 1.6 nm gate oxides and various gate widths. In this work, a small gate-width device with a large drain current density was observed to suffer from serious hot-carrier-induced degradation. By inspecting the gate current (I G) degradation, the quality of gate oxide was observed to decay apparently after hot-carrier stressing. For a 90 nm BC-SOI nMOSFET of 1.2 µm narrow gate width, the tolerance of 1.6 nm ultra thin gate oxide layer was very low particularly around the channel edge region; thus, device reliability is very critical and easily degraded because of device gate oxide breakdown after hot-carrier stressing.

The impacts of high tensile stress CESL and geometry design on device performance and reliability for 90nm SOI nMOSFETs

“…In the subthreshold region, owing to larger channel current density, device with narrow width possesses offstate leakages; thus degrading subthreshold slope and lowering the threshold voltage as shown in Fig. 7(b) [27]. In Fig.…”

A test structure to separately analyze CMOSFET reliabilities around center and edge along the channel width

“…Until now, the reliability comparison between the buried-and the surface-channel narrow-width p-MOSFETs fabricated by STI was reported [9]. Furthermore, the channelwidth dependences of the hot-carrier induced degradation have been studied for n-MOSFETs [6] and SOI n-MOSFETs [10], in which the narrow-width devices had inferior reliability due to the accelerated hot-carrier generation and the injection rates at the channel-region adjacent to the STI edge, and due to the lower gate-oxide-breakdown caused by the large edge current after the hot-carrier stressing around the channel-edge region, respectively. Consequently, twodimensional (2-D) analyses of the hot-carrier effects along the channel-width direction are necessary to realize high reliability CMOSFETs.…”