Wire bonding process impact on low-k dielectric material in damascene copper integrated circuits

Kripesh, V.; Sivakumar, M.; Lim, Loon Aik; Kumar, R.; Iyer, M.K.

doi:10.1109/ectc.2002.1008203

Cited by 25 publications

(8 citation statements)

References 5 publications

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“…Gonzalez et al [5] analyzed the effect of ultrasonic frequency on aluminum wedge bonds. Kripesh et al [6] discussed the optimized process of wirebonding on the Cu/low-K structure. The process parameters were studied with emphasis on free air ball formation, first bond and wedge bond.…”

Section: Introductionmentioning

confidence: 99%

Transient analysis of the impact stage of wirebonding on Cu/low-K wafers

Yeh

Lai

2005

Microelectronics Reliability

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Section: Introductionmentioning

confidence: 99%

Transient analysis of the impact stage of wirebonding on Cu/low-K wafers

Yeh

Lai

2005

Microelectronics Reliability

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“…The introduction of harder 2N gold wire makes it more different to resolve all those issues. Bonding over such low modulus materials has caused the top metallization layer to cup and deflect under the ball, and potential ILD layer delamination during assembly or reliability testing may occur [4,5,6].…”

Section: Introductionmentioning

confidence: 99%

Low K CMOS90 2N gold wire bonding process development

Han¹,

Yan²

2009

2009 International Conference on Electronic Packaging Technology &Amp; High Density Packaging

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The electronics industry is mainly driven by the demand for smaller, faster, higher complexity, more reliable and cheaper device. Reduction in bond pad patch and low K wafer were introduced into mass production for miniaturation and signal transmission integrity. High safety requirement and longer working life demand high reliability performance especially in automotive and aerospace filed. Although trends in electronic packing have been focused on the development of flip chip, Wire bonding still cements its position in chip interconnection technology. In IC assembly, gold wire is the key material in wire bonding process to connect chip to substrate. 2N gold wire with specific dopant is applied in many types of package for stringent reliability requirement field. This study will focus on 2N gold wire application in wire bonding process.Bonding wire, bonding capillary, and wire bonding parameters, was selected as critical factors in this study. This paper describes the key 1st bond parameter optimization on CMOS90 low K device. Gold wire and capillary design were studied. Tail scrubs function of KNS maxum plus wire bonder was also studied to find out how to produce robust 2nd bond. The Newly-designed capillary from SPT aimed to improve wire stitch pull strength was also studied to improve 2N gold wire 2nd bond stitch bond which have weak stitch bond strength result from its big hardness. Critical responses such as Ball size, Ball height bonded ball diameter ratio, bonded ball placement, wire pull strength, ball shear strength, and stitch pull strength were studied to understand the wire bonding effect of low k device. DOE (Design of Experiment) and RSM (response surface methodology) was used to optimize the wire bond process. Thermal aging test coupled with wire pull and ball shear test with recording failure mode were studied. The IMC (Inter Metallic Coverage) of the Au-Al and cratering were also tested.The combination of the low K material and harder 2N wire introduction leaves a narrow process window for packaging assembly, and raises challenges to wire bonding process in terms of process manufacturability. The studies showed that 2N wire were found to be a good replacement of traditional 3N wires on improving bonding integrity of the low K device. Capillary geometry design is also critical to achieve a better IMC coverage, robust 2nd bond. The newly-designed capillary from SPT aimed to improve 2N wire stitch pull strength.

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“…The shrinking of IC dimension beyond 100nm node pitch has required the use of Low K (dielectric) material to replace the traditional SiO2 in order to minimize interconnect delay [1]. The use of porous material as dielectric has imposed significant challenge in package assembly, not only for wafer dicing and wire bonding, but also for package encapsulation.…”

Section: Introductionmentioning

confidence: 99%

Mold process development of C90 LowK and ultra-finepitch BGA for robust reliability performance

Ibrahim¹,

Low²,

Zi-Song³

2009

2009 11th Electronics Packaging Technology Conference

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The use of porous material as dielectric for C90 has imposed significant challenge for package encapsulation due to its porous nature which requires extremely low stress condition under thermal excursion. This paper discussed the challenges in defining the critical characteristics in packaging with special emphasis on molding process in order to achieve robust and reliable package. Key challenges in this particular development was imposed by the increase in package body size, the tightening in wirebond pitch, increased in wire count and tiers, and the inclusion of metal heat spreaders. These factors have significant impact on the mold compound flow and the distribution of filler in the molded package which was found to be responsible for delamination and electrical failure. The resolution to the problem focused on the reduction in average filler size and distribution to improve filler and matrix composition across the molded region. The improvement in these areas has enabled the package to surpass 1000 cycles of temperature cycling and met qualification reliability stress requirement.

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Wire bonding process impact on low-k dielectric material in damascene copper integrated circuits

Cited by 25 publications

References 5 publications

Transient analysis of the impact stage of wirebonding on Cu/low-K wafers

Transient analysis of the impact stage of wirebonding on Cu/low-K wafers

Low K CMOS90 2N gold wire bonding process development

Mold process development of C90 LowK and ultra-finepitch BGA for robust reliability performance

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