Wire Retiming Problem With Net Topology Optimization

Abstract

Abstract-In this paper, we study the retiming problem of sequential circuits with net topology optimization. Both interconnect and gate delay are considered in retiming. Most previous retiming algorithms have assumed ideal conditions for the nonlogical portions of data paths, which are not sufficiently accurate to be used in high performance circuits today. In our modeling, we assume that the delay of a wire is directly proportional to its length. This assumption is reasonable since the quadratic component of a wire delay is significantly smaller than its linear component when the more accurate Elmore delay model is used. A simple experiment was conducted to illustrate the validity of this assumption. We present two approaches to solve the retiming problem, both of which have polynomial time complexity. The first one can compute the optimal clock period while the second one is an improvement over the first one in terms of practical applicability. The second approach gives solutions very close to the optimal (0.06% more than the optimal on average) but in a much shorter runtime. The optimally retimed circuit will then be realized physically by placing the registers and finding the net topologies. In contrast to many previous works [1], [2] that performed simple calculations to determine the register positions, our approach can preserve the optimal clock period obtained by the retiming step and utilize as few registers as possible. Minimization of register number saves both area and power in register and clock loading. Our topology optimization step is shown to be optimal for nets with four or fewer pins and this type of nets constitutes over 90% of the nets in a sequential circuit on average.Using the ISCAS89 benchmark, we tested our algorithm with a 0.35µm CMOS standard cell library. Silicon Ensemble was used to layout the design with row utilization of 50%. Experimental results showed that our algorithm could find the best sharing of registers for a net in most of the cases, i.e., using the minimum number of registers while preserving the target clock period obtained by the retiming step, within a minute run on an Intel Pentium IV 1.5GHz PC with 512MB RAM.

Re-synthesis for cost-efficient circuit-level timing speculation

“…First, to show the efficiency of our FF relocation heuristic, we compare the number of suspicious FFs before and after retiming by using both mathematical programming (derived from [14] and [22]) and the proposed heuristic method for some circuits in Table 1. Column 2, 3, 5 and 6 show the number of suspicious FFs before/after retiming by these two methods and column 3 and 6 represent the runtime respectively.…”

“…The gate delay information is from FSC0G_D 0.13um Standard Cell. The interconnect delay is assumed to be proportional to the distance between two gates after placement [22], which is generated by the open source Capo 10.5 placer [24]. For linear programming solver, we use MATLAB with YALMIP toolbox.…”

“…Mixed integer linear programming (MILP) based approaches for retiming [14,15,22,23] can be used for suspicious FF reduction, by simply changing the objective function in the mathematical programming model. However, this method is not scalable with the increase of circuit size, and at the same time, retiming FFs globally may change the circuit structure a lot, which is not desirable from designers' viewpoint.…”