Wireless Sensor Network Motes: A Comparative Study

Bhat, Ab Wahid; Passi, Abhiruchi

doi:10.23919/indiacom54597.2022.9763269

Cited by 3 publications

(1 citation statement)

References 8 publications

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“…But, the area is so high due to the usage of the structural adders (Chen et al , 2018). In Bhat et al (2015), less-power FIR filter design is implemented on the FPGA platform for wireless communication applications, but it consumed more hardware cost (Tsao and Choi, 2010). In Mittal et al (2017), the FIR filter required a high sampling rate which complicated the filter operation.…”

Section: Introductionmentioning

confidence: 99%

Design and implementation of high-speed and low-power consumption Moore-based loopback adder on FPGA

Kumar¹,

Rangaraju²

2021

IJIUS

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PurposeFinite impulse response (FIR) digital filters are a general element in several digital signal processing (DSP) systems. In VLSI platform, FIR is a developing filter because the complexity of design grows with the length of the FIR filter and also it has less latency. Generally, the FIR filter is designed dominated by the multiplier and adder. The conventional FIR filters occupy more area because of several numbers of adders and multipliers for filter designs.Design/methodology/approachTo overcome this issue, the Vedic Multiplier (VM) and Moore-based LoopBack Adder (MLBA) approach-based optimal FIR filter were designed in this research. Normally, the coefficient has been generated manually, which performs the FIR filter operation. So, the coefficient was generated from the MATLAB filter design and analysis tool. All pass coefficient was introduced in this research, which performs the processing element (PE). The VM approach was utilized in the PE to multiply the filter inputs and coefficients. This research employs the Moore-based LBA (MLBA) in the accumulator for the adding output of the PE. An MLBA approach is a significantly reduced area and increases speed by applying a looping transform function. Here, the proposed method is called a VM-MLBA-FIR filter. In this research, the FIR filter was done in Field Programmable Gate Array (FPGA) Xilinx by using Verilog code on various Virtex devices.FindingsThe experiment results showed that VM-MLBA-FIR filter reduced 26.88% of device utilization and 0.32 W of minimum power consumption compared to the existing PSA-FIR filter.Originality/valueThe experiment results showed that VM-MLBA-FIR filter reduced 26.88% of device utilization and 0.32 W of minimum power consumption compared to the existing PSA-FIR filter.

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Section: Introductionmentioning

confidence: 99%

Design and implementation of high-speed and low-power consumption Moore-based loopback adder on FPGA

Kumar¹,

Rangaraju²

2021

IJIUS

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Processor Optimization of an Energy-Efficient NDIR CO₂ Wireless Sensor Node

Núñez-Prieto¹,

Castells-Rufas

Avellana³

et al. 2022

2022 37th Conference on Design of Circuits and Integrated Circuits (DCIS)

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False Event Message Detection Robust to Burst Attacks in Wireless Sensor Networks

Sei

Ohsuga

2022

IEEE Open J. Commun. Soc.

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A sensor device can be used to detect target events at low cost. Moreover, there is a significant risk of sensor nodes being compromised or captured within large wireless sensor networks (WSNs). The transmission of valid event messages to users by a WSN can be hindered by network congestion due to false event messages in a compromised node. Several methods are available for detecting false event messages. However, they rely on long bits of authentication codes and hence do not provide a fundamental solution to prevent network congestion.

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Wireless Sensor Network Motes: A Comparative Study

Cited by 3 publications

References 8 publications

Design and implementation of high-speed and low-power consumption Moore-based loopback adder on FPGA

Design and implementation of high-speed and low-power consumption Moore-based loopback adder on FPGA

Processor Optimization of an Energy-Efficient NDIR CO₂ Wireless Sensor Node

False Event Message Detection Robust to Burst Attacks in Wireless Sensor Networks

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Wireless Sensor Network Motes: A Comparative Study

Cited by 3 publications

References 8 publications

Design and implementation of high-speed and low-power consumption Moore-based loopback adder on FPGA

Design and implementation of high-speed and low-power consumption Moore-based loopback adder on FPGA

Processor Optimization of an Energy-Efficient NDIR CO2 Wireless Sensor Node

False Event Message Detection Robust to Burst Attacks in Wireless Sensor Networks

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Processor Optimization of an Energy-Efficient NDIR CO₂ Wireless Sensor Node