Within-die process variations: How accurately can they be statistically modeled?

Hargreaves,; Hult,; Reda,

doi:10.1109/aspdac.2008.4484007

Cited by 40 publications

(24 citation statements)

References 17 publications

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“…As introduced before, local variations are difficult to capture, especially in the presence of strong spatial correlation. Following [4] [21] [22] the die can be considered as consisting of a grid of 1 2 n n × locations. A location on the chip will be denoted by ( )…”

Section: Parameter Variations and Uncertainties Characterizationmentioning

confidence: 99%

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Robust Optimization for Gate Sizing Considering Non-Gaussian Local Variations

Roveda¹

2014

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This paper employs a new second-order cone (SOC) model as the uncertainty set to capture non-Gaussian local variations. Then using robust gate sizing as an example, we describe the detailed procedures of robust design with a budget of uncertainty. For a pre-selected probability level of yield protection, this robust method translates uncertainty budgeting problems into regular robust optimization problems. More importantly, under the assumption of non-Gaussian distributions, we show that within-die variations will lead to varying sizes of uncertainty sets at different nominal values. By using this new model of uncertainty estimation, the robust gate sizing problem can be formulated as a Geometric Program (GP) and therefore efficiently solved.

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Section: Parameter Variations and Uncertainties Characterizationmentioning

confidence: 99%

“…In addition, [4] and [5] have pointed out that it is not accurate to use Gaussian distribution to model local variations. In particular, [4] suggested a new statistical model, the Matern model, to capture the local variations based on the measurement data for 90 nm chips. The contributions of this paper can be summarized as follows.…”

Section: Introductionmentioning

confidence: 99%

Robust Optimization for Gate Sizing Considering Non-Gaussian Local Variations

Roveda¹

2014

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“…In order to model the spatial non-uniformity of L ef f as well as its correlation we have used Gaussian Random Fields (GRF) [35]. When using GRF, with stationary and isotropic fields [35] [92], the variance (σ 2 i ) of the random field L(x, y), representing transistor gate length (L ef f ) in the (x,y) die position, depends only on the euclidean distance between two given locations.…”

Section: Modeling Wire Dimension Variationmentioning

confidence: 99%

“…When using GRF, with stationary and isotropic fields [35] [92], the variance (σ 2 i ) of the random field L(x, y), representing transistor gate length (L ef f ) in the (x,y) die position, depends only on the euclidean distance between two given locations. Then, the gate length distribution (L) only depends on a correlation function.…”

Section: Modeling Wire Dimension Variationmentioning

confidence: 99%

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Addressing Manufacturing Challenges in NoC-based ULSI Designs

Luz¹

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ii AgradecimientosVarios han sido los años de mi vida que he dedicado a la realización de esta tesis. Durante estos años si bien he conseguido compaginar mi vida personal con el desarrollo de la la tesis, ha sido el doctorado el que ha marcado de algún modo u otro los tiempos en mi vida. Por todo esto y por mucho más agradezco a Anna la paciencia que durante todos estos años me ha mostrado. Sin su cariño y comprensión la realización de la tesis hubiera sido sin duda un proceso mucho más tortuoso. También aprovecho para agradecer a mis padres que en todo momento me incentivaran a llegar siempre lo más lejos posible en la formación académica. En numerosas ocasiones a lo largo de la tesis me he preguntado si todo esto realmente vale la pena. Ahora con perspectiva y la tesis bajo el brazo todo se ve distinto.Por otro lado me gustaría agradecer a Federico Silla, Vicente Santonja y José Duato la oportunidad que me brindaron para realizar el doctorado en Informática en el Grupo de Arquitecturas Paralelas. Quisiera agradecer especialmente a Fede la ayuda que me ha prestado durante estos años y que ha sido fundamental para la realización de la tesis.Aunque una tesis supone un importante sacrificio personal, no hay que obviar que para la realización de la misma he contado con la inestimable ayuda de muchos compañeros de laboratorio. Durante la etapa inicial de mi doctorado fueron Ricardo, Blas, Crispin, Gaspar, Andres, Paco, Hector, Rafa, David y Noel mis compañeros en el GAP. Con ellos he compartido buenos momentos dentro y fuera del laboratorio. Recuerdo con especial cariño las innumerables ocasiones en las que Hector y yo ( al principio con la compañía de David) maldijimos el día en el que decidimos hacer la tesis. Cinco años después esta etapa ha acabado y una nueva empieza en Barcelona. Más tarde iii iv la incorporación de Toni, con el que ya compartí buenos momentos en los trabajos de Microelectrónica de Teleco, ha sido un apoyo fundamental a la hora de afrontar los problemas que desde el lado oscuro, en el cual mi tesis se ha desarrollado, han ido surgiendo. Finalmente nuevos compañeros de laboratorio como Javi, Knut, Mario, Alberto... han hecho posible que el ambiente del laboratorio siga tan bueno como siempre.Porúltimo no podía olvidarme de agradecer a mis amigos; a los que son heavies y a los que son flamencos, a los que disfrutan de la escalada y a los playeros, a los de la facultad y a los que no han estudiado, que hayan hecho que el tiempo que ha durado la tesis pase tan rápido. Sin duda he disfrutado mucho durante todo este tiempo.

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Implantable neurotechnologies: a review of integrated circuit neural amplifiers

Greenwald

et al. 2016

Med Biol Eng Comput

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Neural signal recording is critical in modern day neuroscience research and emerging neural prosthesis programs. Neural recording requires the use of precise, low-noise amplifier systems to acquire and condition the weak neural signals that are transduced through electrode interfaces. Neural amplifiers and amplifier-based systems are available commercially or can be designed in-house and fabricated using integrated circuit (IC) technologies, resulting in very large-scale integration or application-specific integrated circuit solutions. IC-based neural amplifiers are now used to acquire untethered/portable neural recordings, as they meet the requirements of a miniaturized form factor, light weight and low power consumption. Furthermore, such miniaturized and low-power IC neural amplifiers are now being used in emerging implantable neural prosthesis technologies. This review focuses on neural amplifier-based devices and is presented in two interrelated parts. First, neural signal recording is reviewed, and practical challenges are highlighted. Current amplifier designs with increased functionality and performance and without penalties in chip size and power are featured. Second, applications of IC-based neural amplifiers in basic science experiments (e.g., cortical studies using animal models), neural prostheses (e.g., brain/nerve machine interfaces) and treatment of neuronal diseases (e.g., DBS for treatment of epilepsy) are highlighted. The review concludes with future outlooks of this technology and important challenges with regard to neural signal amplification.

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Within-die process variations: How accurately can they be statistically modeled?

Cited by 40 publications

References 17 publications

Robust Optimization for Gate Sizing Considering Non-Gaussian Local Variations

Robust Optimization for Gate Sizing Considering Non-Gaussian Local Variations

Addressing Manufacturing Challenges in NoC-based ULSI Designs

Implantable neurotechnologies: a review of integrated circuit neural amplifiers

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