Within-wafer CD variation induced by wafer shape

Huang, Chi‐Hsiang; Yang, Mars; Yang, Elvis; Yang, Tahone; Chen, K. C.

doi:10.1117/12.2216048

Cited by 5 publications

(7 citation statements)

References 1 publication

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“…In order to facilitate the evolution to higher density and lower cost of flash memory, a significant step is underway: replacement of 2D NAND with 3D NAND [1][2][3][4][5][6]. As introduced, 3D NAND raises a lot of new issues regarding their fabrication, such as the multi-layer thickness [7], staircase formation [8,9], ultra-high aspect ratio channel hole etch [10][11][12], stress [13][14][15], process detection [16,17] et al In this paper, the * Authors to whom any correspondence should be addressed. challenges of pre-metal dielectric (PMD) oxide in 3D NAND are discussed.…”

Section: Introductionmentioning

confidence: 99%

Pre-metal dielectric PE TEOS oxide pitting in 3D NAND: mechanism and solutions

Hong¹,

Xu²,

Hou³

et al. 2021

Semicond. Sci. Technol.

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In 3D NAND, as the stack number increases, the process cost becomes higher and higher, and the stress problem becomes more and more serious. Therefore, the low cost and low stress plasma enhanced Tetraethyl orthosilicate (PE TEOS), compared to high density plasma (HDP) oxide, shows its superiority as pre-metal dielectric (PMD) oxide layer in 3D NAND. This paper explores the challenges in the application of PE TEOS in 3D NAND PMD oxide layer.In our experiments, both PE TEOS and HDP are employed as the PMD oxide for 3D NAND staircase protection. There is not any void found in the two oxide structures. However, oxide pitting is spotted in the subsequent diluted hydrofluoric acid wet etching in the PE TEOS split. Moreover, we observe that the top silicon nitride corrodes in hot phosphoric acid. We investigate the mechanism of PE TEOS oxide pitting and silicon nitride corroding, and propose two solutions: 1) HDP oxide + PE TEOS, and 2) PE TEOS + dry etching.Experimental results demonstrate that our solutions can well address the issue of PE TEOS oxide pitting and effectively protect the staircase structure. This work extends the application of PE TEOS oxide of which the cost and the stress are both low in 3D NAND.

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Section: Introductionmentioning

confidence: 99%

Pre-metal dielectric PE TEOS oxide pitting in 3D NAND: mechanism and solutions

Hong¹,

Xu²,

Hou³

et al. 2021

Semicond. Sci. Technol.

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“…The 3D NAND has become a mainstream technology in flash memory [1]- [6]. However, with the increase of the stack numbers, more and more challenges have been arising in the manufacturing of 3D NAND, such as the control of multilayer thickness [7], precision and cost for forming staircase patterns [8]- [11], etch of channel hole with ultra-high aspect ratio [12]- [15], stress engineering [16]- [18], and defect detection [19] etc. Among them, the formation and measurement of staircase patterns precisely is a more and more challenging task as the evolution of 3D NAND technology.…”

Section: Introductionmentioning

confidence: 99%

An Improved Dimensional Measurement Method of Staircase Patterns With Higher Precision in 3D NAND

et al. 2020

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3D NAND is a great architectural innovation in the field of flash memory. The staircase for control gate is a unique and important process in the manufacturing of 3D NAND. The staircase is employed to form the electrical connection between the control gate and contact. The current method used to measure the dimension of staircase patterns is, however, not precise enough for the development of state-of-the-art 3D NAND. In this circumstance, an accurate measurement of dimension for as-formed staircase patterns is of great importance and technical interest. In this paper, an improved measurement method is proposed to meet the requirement for higher precision. By taking the overlay into account, a calculation formula for measuring the dimensional error of as-formed staircase is derived for the first time. Two kinds of anchor design (convex SS0 and concave SS0) are put forward to perform dedicated experiments. Achieved results show that the measurement error of as-formed staircase using this improved method is improved from 31.6 nm for normal measurement method to 14.1 nm. The dimensional uniformity of as-formed staircase is therefore improved significantly which in turn leads to well controlled word line leakage. Furthermore, in advanced staircase structure of stair divided scheme (SDS), the convex SS0 shows an advantage in cost compared to the concave SS0.INDEX TERMS 3D NAND, staircase, large dimension measurement, high precision.

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“…Residual stresses can further result in stack deformation, substrate distortion, and even cracking of the film or substrate [4], [5]. In this respect, 3D NAND technologies utilizing vertically stacked memory cells, to increase bit density, were more vulnerable to stress issues [5]- [7]. Specifically, the increased metal gate volume greatly influences the residual stress in the device by contributing to wafer bending, which therefore degrades the uniform depth of focus (DOF) required in the lithography process [1], [6], [7].…”

Section: Introductionmentioning

confidence: 99%

“…In this respect, 3D NAND technologies utilizing vertically stacked memory cells, to increase bit density, were more vulnerable to stress issues [5]- [7]. Specifically, the increased metal gate volume greatly influences the residual stress in the device by contributing to wafer bending, which therefore degrades the uniform depth of focus (DOF) required in the lithography process [1], [6], [7]. In additions, residual stress also enhances the non-uniformity in physical parameters, which is one of the causes of deterioration of device performance and reliability [4], [8].…”

Section: Introductionmentioning

confidence: 99%

The Effect of Tungsten Volume on Residual Stress and Cell Characteristics in MONOS

Sim

Kino

et al. 2019

IEEE J. Electron Devices Soc.

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The effect of residual stress during the tungsten deposition process were investigated using metal-oxide-nitride-oxide-semiconductor (MONOS) devices. The variation of residual stress due to tungsten volume was measured under tensile and compressive stress conditions. Residual stress increased in proportion to the deposition volume. Stress influenced the Si/SiO 2 interface and caused deterioration of the electrical properties, which was experimentally observed during measurements of the interface trap densities and memory windows. We confirmed that residual stress led to degradation of the cell characteristics of MONOS devices, and the absolute value of stress significantly affected these issues regardless of the polarity. From our experiments results, we can predict the degradation of cell characteristics in memory devices, and confirm the need for appropriate stress control in manufacturing process.INDEX TERMS Residual stress, tungsten volume, curvature method, interface trap densities, MONOS structure.

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Within-wafer CD variation induced by wafer shape

Cited by 5 publications

References 1 publication

Pre-metal dielectric PE TEOS oxide pitting in 3D NAND: mechanism and solutions

Pre-metal dielectric PE TEOS oxide pitting in 3D NAND: mechanism and solutions

An Improved Dimensional Measurement Method of Staircase Patterns With Higher Precision in 3D NAND

The Effect of Tungsten Volume on Residual Stress and Cell Characteristics in MONOS

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