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As the semiconductor feature size continues to shrink, the high NA lithography has become a reality. Coupling with high NA lithography, both the critical dimension control and the insufficient resist thickness for etch mask are becoming major challenges for lithographers. Hence two things are highly desired, one is an effective anti-reflective coating (ARC) strategy to maintain low reflectance for good critical dimension (CD) uniformity (CDU) control, and the other is combined ARC and hard-mask concept to satisfy both lithography and etch performance needs for feature patterning.In this study, a dual dielectric anti-reflective coating (dual-DARC) was first demonstrated as an effective ARC for contact application with high NA lithography. The ordinary single DARC is very sensitive to the thickness variation of underlying films, resulting in a >45nm contact CD variation at interlayer dielectric (ILD) thickness variation of ±150nm induced by CMP process. Unlike the single DARC, the dual-DARC performs a less CD variation of ~5nm at the same film thickness variation. By extending the dual-DARC concept to combined ARC/hard-mask application to contact and poly patterning, several ARC/hard-mask schemes were compared by reflectance control, CD uniformity control and etch hard-mask performance. Apart from the good reflectance and CD uniformity control of dual-DARC-like schemes, the most attractive is that the proper use of dual-DARC concept to hard-mask application, the tight thickness control is not necessary for the bottom layer and you can just tailor the bottom layer's thickness to meet the individual process needs.

DPS (Double Patterning with Spacer) has been one of the most promising solutions in flash memory device manufacturing. Apart from the process complexity inherent with the DPS process, the DPS process also requires more engineering efforts on alignment technique compared to the single patterning. Since the traditional alignment marks defined by the core mask has been altered hence the alignment mark recognition could be challenging for the subsequent process layers.This study characterizes the process influence on the traditional ASML VSPM (Versatile Scribelane Primary Marks) alignment mark, and various types of sub-segmentations within VSPM marks were carried out to enable the alignment and find out the best performing alignment marks. The design of the transverse and vertical sub-segmentations within the VSPM marks is aimed to enhance the alignment signal strength and mark detectability. Alignment indicators of WQ (Wafer Quality), MCC (Multiple Correlation Coefficient) and ROPI (Residual Overlay Performance Indicator) were used to judge the alignment performance and stability. A good correlation was established between sub-segmentations and wafer alignment signal strength.