Wordlength as an Architectural Parameter for Reconfigurable Computing Devices

Stansfield, Tony

doi:10.1007/3-540-46117-5_69

Cited by 2 publications

(2 citation statements)

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“…6. The choice of 4-bits as a granularity of the logic block is dictated by the fact that such granularity has been found the most optimal for the datapath mapping [6] [23].…”

Section: Logic Block Structurementioning

confidence: 99%

An FPGA architecture with enhanced datapath functionality

Leijten-Nowak

Meerbergen

2003

Proceedings of the 2003 ACM/SIGDA Eleventh International Symposium on Field Programmable Gate Arrays

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Although FPGAs are a cost-efficient alternative for both ASICs and general purpose processors, they still result in designs which are more than an order of magnitude more costly and slower than their equivalents implemented in dedicated logic. This efficiency gap makes FPGAs less suitable for high-volume cost-sensitive applications (e.g. embedded systems).We show that the intrinsic cost of traditional general-purpose FPGAs can be reduced if they are designed to target an application domain or a class of applications only. We propose a method of the application-domain characterization and apply it to characterize DSP. A novel FPGA logic block architecture derived based on such an analysis, and which exploits properties of target applications, is presented. Its key feature is the 'mixed-level granularity' being a trade-off between fine and coarse granularity required for the implementation of datapath and random logic functions, respectively. This leads to a factor of four improvement in the LUT memory size compared to commercial FPGAs, and, assuming a standardcell implementation, a 1.6-2.8 lower datapath mapping cost. A modified mixed-grain architecture with the ALU-like functionality reduces the LUT memory size by a factor of 16 compared to commercial FPGAs, and mapped onto standard cells has a 1.9-3.3 times higher datapath mapping efficiency. For these reasons, the proposed FPGA architectures may be an interesting alternative to the traditional general-purpose FPGA devices, especially if characteristics of a target application domain are known a priori.

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“…6. The choice of 4-bits as a granularity of the logic block is dictated by the fact that such granularity has been found the most optimal for the datapath mapping [6] [23].…”

Section: Logic Block Structurementioning

confidence: 99%

An FPGA architecture with enhanced datapath functionality

Leijten-Nowak

Meerbergen

2003

Proceedings of the 2003 ACM/SIGDA Eleventh International Symposium on Field Programmable Gate Arrays

View full text Add to dashboard Cite

show abstract

“…In contrast to the conventional bit-level processing, some FPGAs have been made to operate on wider (multi-bit) arguments. Because of the cost-efficiency tradeoff it offers [23], a 4-bit processing has been particularly popular [16][6] [15]. Also, in many commercial general-purpose FPGA devices very coarse logic blocks have been used to allow the generation of multi-bit results in one processing element, and, at the same time, the reduction of the routing resource complexity [27] [3].…”

Section: Previous Workmentioning

confidence: 99%