Work-function engineering in gate first technology for multi-V&lt;inf&gt;T&lt;/inf&gt; dual-gate FDSOI CMOS on UTBOX

Weber, O.; Andrieu, F.; Mazurier, J.; Cassé, M.; Garros, X.; Leroux, C.; Martín, F.; Perreau, P.; Fenouillet-Béranger, C.; Barnola, S.; Gassilloud, R.; Arvet, C.; Thomas, Olivier; Noël, J.‐P.; Rozeau, O.; Jaud, M.-A.; Poiroux, T.; Lafond, D.; Toffoli, A.; Allain, F.; Tabone, C.; Tosti, L.; Brévard, L.; Lehnen, P.; Weber, U.; Baumann, P. K.; Boissière, Olivier; Schwarzenbach, W.; Bourdelle, K.K.; Nguyen, B.-Y.; Bœuf, F.; Skotnicki, T.; Faynot, O.

doi:10.1109/iedm.2010.5703289

Cited by 33 publications

(24 citation statements)

References 0 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Thus, the thicker the buried oxide, the higher the source to drain coupling will be. Scaling down of the buried oxide is mandatory to maintain the electrostatic characteristics of MOSFETs (Figure 6(a)) [25][26][27][28]. Recent results have shown that [29,30]; (b) strained dual channel CMOS process flow [29].…”

Section: Fully Depleted Devices On Insulator Ultra-thin Silicon Thickmentioning

confidence: 95%

Ultra-thin films and multigate devices architectures for future CMOS scaling

Deleonibus

2011

Sci. China Inf. Sci.

View full text Add to dashboard Cite

The nanoelectronics industry is facing historical challenges to scale down CMOS devices to meet demands for low voltage, low power, high performance and increased functionality. Using new materials and devices architectures is necessary. HiK gate dielectrics and metal gates have been introduced and have shown their ability to reduce power consumption. Fully depleted ultra-thin SOI devices are a good alternative to bulk for low power applications. Multigate devices are the current goal in device architecture to increase MOSFET drivability, reduce power, and allow new opportunities for future applications. Thin film based solutions will be necessary in the future because of fundamental limitations on gate capacitance scaling and system integration requirements. Exploiting 3D device stacking via wafer bonding could be a good way to introduce new materials (HiK, strained Si, hybrid orientations, Ge, III-Vs, Carbon-based materials, graphene and CNTs, and functional molecules) and continue increasing integration density. Si based CMOS will be scaled beyond the ITRS as the System-on-Chip/Wafer Platform.The international technology roadmap of semiconductors (ITRS) [1] distinguishes three types of products: high performance (HP), low operating power (LOP) and low standby power (LSTP) devices. In the HP case, a landmark has been reached at the 32-nm node: the contribution from static power dissipation approaches the dynamic power contribution [2]. Multigate devices could improve this somewhat by increasing the saturation current to leakage current ratio.In this review, we will first analyze the primary limitations and showstoppers of CMOS scaling. Issues on gate stack, channel and source and drain engineering as well as new device architectures (FDSOI or multigate devices) are discussed.Low power consumption and heterogeneous function integration will be leveraged by future nomadic systems. The increased number of devices and different types of signals will, in turn, require the leveraging of 3D IN package or ON chip co-integration. Limitations, showstoppers and opportunities of Si CMOS scalingCMOS device engineering consists of minimizing leakage current and the maximization of output current. In sub-100-nm CMOS devices, non-stationary transport is more important than diffusive transport. To this end, several questions arise related to the origins of the leakage currents, non-stationary transport limitations and supply voltage scaling.

show abstract

Section: Fully Depleted Devices On Insulator Ultra-thin Silicon Thickmentioning

confidence: 95%

Ultra-thin films and multigate devices architectures for future CMOS scaling

Deleonibus

2011

Sci. China Inf. Sci.

View full text Add to dashboard Cite

show abstract

“…A straightforward method is the use of different gate materials to tune the gate workfunction, thereby modifying the threshold voltage of the device [3], [13]. Similar as tuning the gate oxide thickness and channel doping concentration to modify , this method requires extra process steps, which affects the layout regularity and increases the process costs compared to single-design.…”

Section: A Conventional Multi-threshold-voltage Technologymentioning

confidence: 99%

“…The threshold voltage of the FDSOI device can be also tuned by properly doping a ground plane layer below the buried oxide [13]. However, this method also requires extra process steps.…”

Section: A Conventional Multi-threshold-voltage Technologymentioning

confidence: 99%

Configurable Circuits Featuring Dual-Threshold-Voltage Design With Three-Independent-Gate Silicon Nanowire FETs

Zhang

Tang

Gaillardon

et al. 2014

IEEE Trans. Circuits Syst. I

View full text Add to dashboard Cite

Abstract-Silicon nanowire transistors with Schottky-barrier contacts exhibit both -type and -type characteristics under different bias conditions. Polarity controllability of silicon nanowire transistors has been further demonstrated by using an additional polarity gate. The device can be configured as -type or -type by controlling the polarity gate voltage. This paper extends this approach by using three independent gates and shows its interest to implement dual-threshold-voltage configurable circuits. Polarity and threshold voltage of uncommitted devices are determined by applying different bias patterns to the three gates. Uncommitted logic gates can thus be configured to implement different logic functions, targeting either high-performance or low-leakage applications. Dual-threshold-voltage design is thereby achievable through the use of a wiring scheme on an uncommitted pattern. With the polarity controllability of the three-independent-gate device, a range of logic functions is also obtained by replacing and GND by complementary input signals. Synthesis results of ISCAS'85 and VTR sequential benchmark circuits with these devices show, before place and route, comparable performance and 51% reduction of leakage power consumption compared to 22-nm low-standby-power FinFET technology.

show abstract

“…1) [8]. Recently this scheme was successfully demonstrated to implement multi-V T options for metalgate/high- MOSFETs using ultrathin body and bottom oxide (UTBB) SOI substrate [9].…”

Section: Introductionmentioning

confidence: 99%

“…2 and Table 1 summarize the model structure used in this study. Based on the recent studies on UTBB-SOI MOSFETs, the baseline device is defined with 6 nm of SOI and 10 nm of BOX with the raised source/drain [9,11]. To maximize the current drivability, the source junction is designed within a narrow bandgap material [12].…”

Section: Introductionmentioning

confidence: 99%

V_T-Modulation of Planar Tunnel Field-Effect Transistors with Ground-Plane under Ultrathin Body and Bottom Oxide

Sun¹,

Kim²,

Kim³

et al. 2014

JSTS:Journal of Semiconductor Technology and Science

View full text Add to dashboard Cite

Abstract-Control of threshold voltage (V T ) by ground-plane (GP) technique for planar tunnel fieldeffect transistor (TFET) is studied for the first time using TCAD simulation method. Although GP technique appears to be similarly useful for the TFET as for the metal-oxide-semiconductor field-effect transistor (MOSFET), some unique behaviors such as the small controllability under weak ground doping and dependence on the dopant polarity are also observed. For V T -modulation larger than 100 mV, heavy ground doping over 1×10 20 cm -3 or back biasing scheme is preferred in case of TFETs. Polarity dependence is explained with a mechanism similar to the punch-through of MOSFETs. In spite of some minor differences, this result shows that both MOSFETs and TFETs can share common V T -control scheme when these devices are co-integrated.Index Terms-Threshold voltage, Tunnel field-effect Transistor (TFET), ground-plane, ultrathin body and bottom oxide (UTBB), TCAD simulation

show abstract

Work-function engineering in gate first technology for multi-V<inf>T</inf> dual-gate FDSOI CMOS on UTBOX

Cited by 33 publications

References 0 publications

Ultra-thin films and multigate devices architectures for future CMOS scaling

Ultra-thin films and multigate devices architectures for future CMOS scaling

Configurable Circuits Featuring Dual-Threshold-Voltage Design With Three-Independent-Gate Silicon Nanowire FETs

V_T-Modulation of Planar Tunnel Field-Effect Transistors with Ground-Plane under Ultrathin Body and Bottom Oxide

Contact Info

Product

Resources

About

Work-function engineering in gate first technology for multi-V<inf>T</inf> dual-gate FDSOI CMOS on UTBOX

Cited by 33 publications

References 0 publications

Ultra-thin films and multigate devices architectures for future CMOS scaling

Ultra-thin films and multigate devices architectures for future CMOS scaling

Configurable Circuits Featuring Dual-Threshold-Voltage Design With Three-Independent-Gate Silicon Nanowire FETs

VT-Modulation of Planar Tunnel Field-Effect Transistors with Ground-Plane under Ultrathin Body and Bottom Oxide

Contact Info

Product

Resources

About

V_T-Modulation of Planar Tunnel Field-Effect Transistors with Ground-Plane under Ultrathin Body and Bottom Oxide