Yield model for ASIC and processor chips

Stapper, C.H.; Jansen, Patrick; Rosner, R.J.

doi:10.1109/dftvs.1993.595739

Cited by 12 publications

(6 citation statements)

References 6 publications

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“…Using the adaptive algorithm selection and scheduling, all the nonredundant system configurations have been identified and provided in Table V. The design of fault-tolerant systems with optimal productivity has been performed under various design parameters such as the probability of a good processor, the probability of a good memory unit, the area ratio of processor and memory, as suggested in [20].…”

Section: Resultsmentioning

confidence: 99%

“…adaptive fault-tolerant algorithm selection and scheduling problem, ii. design of fault-tolerant system to optimize productivity [5] which is defined to be the ratio of the relative change in yield [20] over the relative change in area. First, the adaptive fault-tolerant algorithm selection and scheduling problem using the motivational example in Table I are introduced.…”

Section: B Motivational Examplementioning

confidence: 99%

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A Heterogeneous Built-In Self-Repair Approach Using System-Level Synthesis Flexibility

Hong

Potkonjak

Karri³

2004

IEEE Trans. Rel.

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Abstract-Summary and Conclusions -A novel methodology is proposed for designing fault-tolerant real-time multi-processor systems-on-a-chip to achieve optimal productivity. The methodology employs the heterogeneous built-in-self-repair (BISR) based on graceful degradation and yield enhancement techniques as an embedded optimization engine. The technique exploits the flexibility provided in task-level scheduling and algorithm selection steps. A hardware fault model is developed for modern superscalar processors and multi-processors which enables an efficient treatment of the synthesis and compilation goals. For the first time, heterogeneous BISR is used at the task level. The key idea is to adapt scheduling and algorithm selection to the available nonfaulty resources. If there is a fault in memory, the algorithms that use less memory are selected and the scheduler exploits the other abundant resource, viz, the processors, more vigorously to compensate for the loss of part of memory. Similarly, a fault in a processor is backed up by memory. The synthesis approach minimizes the degradation in performance for single or multiple faults using simulated annealing-based algorithm selection, scheduling, and assignment algorithms. On the large set of examples this adaptive algorithm selection and scheduling technique has achieved important improvement of throughput compared to conventional nonadaptive schemes. The experimental results also indicate that important improvement in productivity can be achieved by using the extra throughput gained from the technique.

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Section: Resultsmentioning

confidence: 99%

Section: B Motivational Examplementioning

confidence: 99%

A Heterogeneous Built-In Self-Repair Approach Using System-Level Synthesis Flexibility

Hong

Potkonjak

Karri³

2004

IEEE Trans. Rel.

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“…The average number of experiments, E, that are necessary to deter-mine pass/fail status of each core (up to the choice to exit according to the deration policy) may be calculated as a function of the per core yield, Y. It is pessimistic to assume that the yield of a particular core is the same regardless of whether other cores are defective [11], but let us hold with that pessimistic assumption for the sake of simplicity in this explanation. For this "at least two out of four core" example, Table 2 shows the relative probabilities of all possible experimental outcomes.…”

Section: Inter-core Compare Modementioning

confidence: 99%

“…Given a failing cycle number (FailCycle), the resulting core-level failing cycle number (FailCycle core ) is calculated according to formula (11). …”

Section: Fail Data Translationmentioning

confidence: 99%

Test Access Mechanism for Multiple Identical Cores

Giles

Wang

Sehgal

et al. 2008

2008 IEEE International Test Conference

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A new test access mechanism (TAM) for multiple identical embedded cores is proposed. It exploits the identical nature of the cores and modular pipelined circuitry to provide scalable and flexible capabilities to make tradeoffs between test time and diagnosis over the manufacturing maturity cycle from low-yield initial production to high-yield, high-volume production. The test throughput gains of various configurations of this TAM are analyzed. Forward and reverse protocol translations for core patterns applied with this TAM are described.

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“…For example, it can be assumed that only one defect exists in a fabricated circuit which results in a single gate delay fault. This assumption, referred to as single gate delay fault assumption (SGDF), is a realistic assumption because for any process with reasonable yield, it is very unlikely that multiple defects exist in a fabricated circuit [5] [6]. Traditional transition fault model [7] and gate delay fault model [8] [9] are also based on this assumption.…”

Section: Introductionmentioning

confidence: 99%

Improving Timing-Independent Testing of Crosstalk Using Realistic Assumptions on Delay Faults

Irajpour

Gupta

Breuer

2007

16th Asian Test Symposium (ATS 2007)

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Test generation methodology previously developed for crosstalk targets in the presence of manufacturing defects and process variations results in low coverage. In this paper, under a realistic assumption about the nature of manufacturing defects, we show that by incorporating two new concepts, namely, noncriticality and delay-superiority, significantly higher coverage of targets and lower test generation and test application costs are achieved.

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Yield model for ASIC and processor chips

Cited by 12 publications

References 6 publications

A Heterogeneous Built-In Self-Repair Approach Using System-Level Synthesis Flexibility

A Heterogeneous Built-In Self-Repair Approach Using System-Level Synthesis Flexibility

Test Access Mechanism for Multiple Identical Cores

Improving Timing-Independent Testing of Crosstalk Using Realistic Assumptions on Delay Faults

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