Yield Model for Productivity Optimization of VLSI Memory Chips with Redundancy and Partially Good Product

Repairing embedded memories (e-memories) on an advanced system-on-chip (SOC) product is a key technique used to improve product yield. However. increasing the die area of SOC products equipped with various types of e-memories on the die is an issue. A fuse scheme can be used to resolve this issue. However. several fuse schemes that have been proposed to decrease the die area result in an increased repair time. Therefore. in this paper. we propose a novel fuse scheme that decreases both die area and repair time. Moreover. our approach is applied to a 65 nm SoC product. The results indicate that the proposed fuse scheme effectively decrea~es the die area and repair time of advanced SOC products. key words: ralld(}m access mem(}l)~ system-em-chip. redulldallcy.juse

show abstract

“…According to the conventional statistical yield model [15]- [ 19]. the probability PIO(X) of x IDs failures occurring is given by…”

Section: Optimizing Virtual E-memory Groupsmentioning

confidence: 99%

Novel Fuse Scheme with a Short Repair Time to Maximize Good Chips per Wafer in Advanced SoCs

Matsumoto

Hamamura

Nakao

et al. 2013

IEICE Trans. Electron.

View full text Add to dashboard Cite

show abstract

“…Let us also assume the well-known yield formula due to Stapper [21], [22] to calculate the original yield of the memory array without built-in self-repair where is the defect density, is the area of the RAM array, and is some clustering factor of the defects. Let be the probability function for a defect pattern to be repairable with respect to the fault-free spare rows available.…”

Section: Yield Improvementmentioning

confidence: 99%

A physical design tool for built-in self-repairable RAMs

Chakraborty

Kulkami

Bhattacharya

et al. 2001

IEEE Trans. VLSI Syst.

View full text Add to dashboard Cite

Abstract-In this paper, we present the description and evaluation of a novel physical design tool, BISRAMGEN, that can generate reconfigurable and fault-tolerant RAM modules. This tool, first proposed in [3], designs a redundant RAM array with accompanying built-in self-test (BIST) and built-in self-repair (BISR) logic that can switch out faulty rows and switch in spare rows. Built-in self-repair causes significant improvement in reliability, production yield, and manufacturing cost of ASICs and microprocessors with embedded RAMs.

show abstract

“…Under proper assumptions each one of these 23 statistics can be used and the "correct" one is the one that fits the data best [43]. One model which has been shown to agree with experimental results, is the generalized negative binomial distribution [42].…”

Section: Analytical Models For Evaluation Of Yield and Performancementioning

confidence: 99%

Yield and Performance Enhancement through Redundancy in VLSI and WSI Multi-Precessor Systems.

Koren¹,

Pradhan²

1986

View full text Add to dashboard Cite

Yield Model for Productivity Optimization of VLSI Memory Chips with Redundancy and Partially Good Product

Cited by 223 publications

References 14 publications

Novel Fuse Scheme with a Short Repair Time to Maximize Good Chips per Wafer in Advanced SoCs

Novel Fuse Scheme with a Short Repair Time to Maximize Good Chips per Wafer in Advanced SoCs

A physical design tool for built-in self-repairable RAMs

Yield and Performance Enhancement through Redundancy in VLSI and WSI Multi-Precessor Systems.

Contact Info

Product

Resources

About