Zero-content augmented caches

Abstract

It has been observed that some applications manipulate large amounts of null data. Moreover these zero data often exhibit high spatial locality. On some applications more than 20% of the data accesses concern null data blocks. Representing a null block in a cache on a standard cache line appears as a waste of resources.In this paper, we propose the Zero-Content Augmented cache, the ZCA cache. A ZCA cache consists of a conventional cache augmented with a specialized cache for memorizing null blocks, the Zero-Content cache or ZC cache. In the ZC cache, the data block is represented by its address tag and a validity bit. Moreover, as null blocks generally exhibit high spatial locality, several null blocks can be associated with a single address tag in the ZC cache.For instance, a ZC cache mapping 32MB of zero 64-byte lines uses less than 80KB of storage. Decompression of a null block is very simple, therefore read access time on the ZCA cache is in the same range as the one of a conventional cache. On applications manipulating large amount of null data blocks, such a ZC cache allows to significantly reduce the miss rate and memory traffic, and therefore to increase performance for a small hardware overhead. In particular, the write-back traffic on null blocks is limited. For applications with a low null block rate, no performance loss is observed.

Toggle-Aware Compression for GPUs

“…Two overheads of compression are well-known: (i) additional data processing due to compression/decompression, and (ii) hardware changes to transfer variable-length cache lines. While these two problems are significant, multiple compression algorithms [2], [27], [18], [9] were proposed to minimize the overheads of data compression/decompression. Several designs [22], [21], [17], [26] were proposed to integrate bandwidth compression into existing memory hierarchies.…”

Concertina: Squeezing in Cache Content to Operate at Near-Threshold Voltage

“…Several compression mechanisms have been proposed in the literature to increase the effective storage capacity of all the on-chip cache levels, potentially reducing misses and improving performance [2], [13], [16], [22], [34], [36], [40]. In general, these proposals seek to maximize the compression ratio either to store more than one block in each cache entry, or to reduce the energy consumption of each LLC access.…”

“…For example, zero is by far the most frequent value in data memory pages: it is used to initialize memory values, and to represent null pointers or false Boolean values, among others. Many compression schemes are based on compressing zeros or treating them as a special case [16], [34], [38], [40]. Exploiting zero redundancy can lead to a simple compression technique.…”

Decoupled zero-compressed memory

“…Only non-zero blocks are really stored in the compressed physical memory (CP memory). Our compressed memory design is inspired by the decoupled sectored cache [12] and the Zero Content Augmented cache [7]. In the (N,P)-decoupled sectored cache, a sector (i.e.…”

“…We propose to leverage this property through the use of a hardware compressed memory that only targets null data blocks, the decoupled zero-compressed memory. Borrowing ideas from the decoupled sectored cache [12] and the zero-content augmented cache [7], the decoupled zero-compressed memory, or DZC memory, manages the main memory as a decoupled sectored set-associative cache where null blocks are only represented by a validity bit.Our experiments show that for many applications, the DZC memory allows to artificially enlarge the main memory, i.e. it reduces the effective physical memory size needed to accommodate the working set of an application without excessive page swapping.…”